Sarthak Antal

According to our database, Sarthak Antal authored at least 4 papers between 2025 and 2026.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2026

Time Domain Near Memory Computing Engine.

Sarthak Antal, Steve Enosh

CoRR, May, 2026

25.3 A 16nm 0.042mm² 0.66μJ/Ops Lightweight MLWE PQC KEM with Cryptanalysis-ASIC Co-Optimization.

Archisman Ghosh, Ming-Che Li, Lingke Ding, Suparna Kundu, Abdullah Sayeed, Angshuman Karmakar, Harshit Naman, Sarthak Antal, Ingrid Verbauwhede, Shreyas Sen

Proceedings of the IEEE International Solid-State Circuits Conference, 2026

A 16nm 0.67pJ/bit 80Mb/s Circuit-System Co-Optimized Time Domain Brain Channel Receiver.

Harshit Naman, Gourab Barik, Sarthak Antal, Samyadip Sarkar, Ming-Che Li, Shreyas Sen

Proceedings of the IEEE Custom Integrated Circuits Conference, 2026

2025

A 54μW Design-Agnostic Clock, Voltage, and EM-Pulse Fault-Injection Attack Detection Using Time-to-Voltage Conversion.

Yudhajit Ray, Archisman Ghosh, Sarthak Antal, Shreyas Sen

Proceedings of the IEEE Custom Integrated Circuits Conference, 2025