Hiok-Tiaq Ng

According to our database, Hiok-Tiaq Ng authored at least 12 papers between 1997 and 2012.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2012

A 48-Port FCC-Compliant 10GBASE-T Transmitter With Mixed-Mode Adaptive Echo Canceller.

Ramin Farjad-Rad, Friedel Gerfers, Michael Brown, Ahmad Tavakoli, David Nguyen, Hossein Sedarat, Ramin Shirani, Hiok-Tiaq Ng

IEEE J. Solid State Circuits, 2012

A 16-port FCC-compliant 10GBase-T transmitter and hybrid with 76dBc SFDR up to 400MHz scalable to 48 ports.

Friedel Gerfers, Ramin Farjad-Rad, Michael Brown, Ahmad Tavakoli, David Nguyen, Hiok-Tiaq Ng, Ramin Shirani

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2004

A 33-mW 8-Gb/s CMOS clock multiplier and CDR for highly integrated I/Os.

Ramin Farjad-Rad, Anhtuyet Nguyen, James Tran, Trey Greer, John Poulton, William J. Dally, John H. Edmondson, Ramesh Senthinathan, Rohit Rathi, Ming-Ju Edward Lee, Hiok-Tiaq Ng

IEEE J. Solid State Circuits, 2004

2003

A second-order semidigital clock recovery circuit based on injection locking.

Hiok-Tiaq Ng, Ramin Farjad-Rad, Ming-Ju Edward Lee, William J. Dally, Trey Greer, John Poulton, John H. Edmondson, Rohit Rathi, Ramesh Senthinathan

IEEE J. Solid State Circuits, 2003

Jitter transfer characteristics of delay-locked loops - theories and design techniques.

Ming-Ju Edward Lee, William J. Dally, Trey Greer, Hiok-Tiaq Ng, Ramin Farjad-Rad, John Poulton, Ramesh Senthinathan

IEEE J. Solid State Circuits, 2003

CMOS High-Speed I/Os - Present and Future.

Ming-Ju Edward Lee, William J. Dally, Ramin Farjad-Rad, Hiok-Tiaq Ng, Ramesh Senthinathan, John H. Edmondson, John W. Poulton

Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

A 33mW 8Gb/s CMOS clock multiplier and CDR for highly integrated I/Os.

Hiok-Tiaq Ng, Ming-Ju Edward Lee, Ramin Farjad-Rad, Ramesh Senthinathan, William J. Dally, Anhtuyet Nguyen, Rohit Rathi, Trey Greer, John Poulton, John H. Edmondson, James Tran

Proceedings of the IEEE Custom Integrated Circuits Conference, 2003

2002

A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips.

Ramin Farjad-Rad, William J. Dally, Hiok-Tiaq Ng, Ramesh Senthinathan, Ming-Ju Edward Lee, Rohit Rathi, John Poulton

IEEE J. Solid State Circuits, 2002

1999

A multistage amplifier technique with embedded frequency compensation.

Hiok-Tiaq Ng, Ramsin M. Ziazadeh, David J. Allstot

IEEE J. Solid State Circuits, 1999

1998

A multistage amplifier topology with embedded tracking compensation.

Ramsin M. Ziazadeh, Hiok-Tiaq Ng, David J. Allstot

Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998

1997

CMOS current steering logic for low-voltage mixed-signal integrated circuits.

Hiok-Tiaq Ng, David J. Allstot

IEEE Trans. Very Large Scale Integr. Syst., 1997

Charge-pump assisted low-power/low-voltage CMOS opamp design.

Jianjun Zhou, Ramsin M. Ziazadeh, H.-H. Ng, Hiok-Tiaq Ng, David J. Allstot

Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997