Ramin Farjad-Rad

According to our database, Ramin Farjad-Rad authored at least 20 papers between 1998 and 2021.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2021

An Open Inter-Chiplet Communication Link: Bunch of Wires (BoW).

Shahab Ardalan, Ramin Farjadrad, Mark Kuemerle, Ken Poulton, Suresh Subramaniam, Bapiraju Vinnakota

IEEE Micro, 2021

An Echo-Cancelling Front-End for 112Gb/s PAM-4 Simultaneous Bidirectional Signaling in 14nm CMOS.

Ramin Farjadrad, Kambiz Kaviani, David Nguyen, Michael Brown, Govert Geelen, Corné Bastiaansen, Narendra Rao, Viswa Popuri, Greg Shen, Hamid Khatibi, Saudas Dey, Anirban Chatterjee, David Shen, Peter Zijlstra, Harrie Gunnink, Kebin Zhang, Venkat Penumuchu, Oliver Weiss, Edward J. F. Paulus, Joost Briaire

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2020

A Bunch-of-Wires (BoW) Interface for Interchiplet Communication.

Ramin Farjadrad, Mark Kuemerle, Bapi Vinnakota

IEEE Micro, 2020

Bunch of Wires: An Open Die-to-Die Interface.

Shahab Ardalan, Halil Cirit, Ramin Farjad-Rad, Mark Kuemerle, Ken Poulton, Suresh Subramanian, Bapiraju Vinnakota

Proceedings of the IEEE Symposium on High-Performance Interconnects, 2020

2019

High Capacity On-Package Physical Link Considerations.

Greg Taylor, Ramin Farjadrad, Bapiraju Vinnakota

Proceedings of the 2019 IEEE Symposium on High-Performance Interconnects, 2019

A Bunch of Wires (BoW) Interface for Inter-Chiplet Communication.

Ramin Farjadrad, Bapiraju Vinnakota

Proceedings of the 2019 IEEE Symposium on High-Performance Interconnects, 2019

2015

10G | 5G | 2.5G | 1G | 100M physical layer PHY: HOT CHIPS 2015 conference.

Ramin Shirani, Ramin Farjad-Rad

Proceedings of the 2015 IEEE Hot Chips 27 Symposium (HCS), 2015

2012

A 48-Port FCC-Compliant 10GBASE-T Transmitter With Mixed-Mode Adaptive Echo Canceller.

Ramin Farjad-Rad, Friedel Gerfers, Michael Brown, Ahmad Tavakoli, David Nguyen, Hossein Sedarat, Ramin Shirani, Hiok-Tiaq Ng

IEEE J. Solid State Circuits, 2012

A 16-port FCC-compliant 10GBase-T transmitter and hybrid with 76dBc SFDR up to 400MHz scalable to 48 ports.

Friedel Gerfers, Ramin Farjad-Rad, Michael Brown, Ahmad Tavakoli, David Nguyen, Hiok-Tiaq Ng, Ramin Shirani

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2011

Low-power high-density 10GBASE-T ethernet transceiver.

Ramin Shirani, Ramin Farjadrad

Proceedings of the 2011 IEEE Hot Chips 23 Symposium (HCS), 2011

2007

A 7.5Gb/s 10-Tap DFE Receiver with First Tap Partial Response, Spectrally Gated Adaptation, and 2nd-Order Data-Filtered CDR.

Brian S. Leibowitz, Jade Kizer, Haechang Lee, Fred Chen, Andrew Ho, Metha Jeeradit, Akash Bansal, Trey Greer, Simon Li, Ramin Farjad-Rad, William F. Stonecypher, Yohan Frans, Barry Daly, Fred Heaton, Bruno W. Garlepp, Carl W. Werner, Nhat Nguyen, Vladimir Stojanovic, Jared Zerbe

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2004

A 33-mW 8-Gb/s CMOS clock multiplier and CDR for highly integrated I/Os.

Ramin Farjad-Rad, Anhtuyet Nguyen, James Tran, Trey Greer, John Poulton, William J. Dally, John H. Edmondson, Ramesh Senthinathan, Rohit Rathi, Ming-Ju Edward Lee, Hiok-Tiaq Ng

IEEE J. Solid State Circuits, 2004

2003

A second-order semidigital clock recovery circuit based on injection locking.

Hiok-Tiaq Ng, Ramin Farjad-Rad, Ming-Ju Edward Lee, William J. Dally, Trey Greer, John Poulton, John H. Edmondson, Rohit Rathi, Ramesh Senthinathan

IEEE J. Solid State Circuits, 2003

Jitter transfer characteristics of delay-locked loops - theories and design techniques.

Ming-Ju Edward Lee, William J. Dally, Trey Greer, Hiok-Tiaq Ng, Ramin Farjad-Rad, John Poulton, Ramesh Senthinathan

IEEE J. Solid State Circuits, 2003

CMOS High-Speed I/Os - Present and Future.

Ming-Ju Edward Lee, William J. Dally, Ramin Farjad-Rad, Hiok-Tiaq Ng, Ramesh Senthinathan, John H. Edmondson, John W. Poulton

Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

A 33mW 8Gb/s CMOS clock multiplier and CDR for highly integrated I/Os.

Hiok-Tiaq Ng, Ming-Ju Edward Lee, Ramin Farjad-Rad, Ramesh Senthinathan, William J. Dally, Anhtuyet Nguyen, Rohit Rathi, Trey Greer, John Poulton, John H. Edmondson, James Tran

Proceedings of the IEEE Custom Integrated Circuits Conference, 2003

2002

A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips.

Ramin Farjad-Rad, William J. Dally, Hiok-Tiaq Ng, Ramesh Senthinathan, Ming-Ju Edward Lee, Rohit Rathi, John Poulton

IEEE J. Solid State Circuits, 2002

2000

A 0.3-μm CMOS 8-Gb/s 4-PAM serial link transceiver.

Ramin Farjad-Rad, Chih-Kong Ken Yang, Mark A. Horowitz, Thomas H. Lee

IEEE J. Solid State Circuits, 2000

1999

A 0.4-μm CMOS 10-Gb/s 4-PAM pre-emphasis serial link transmitter.

Ramin Farjad-Rad, Chih-Kong Ken Yang, Mark A. Horowitz, Thomas H. Lee

IEEE J. Solid State Circuits, 1999

1998

A 0.5-μm CMOS 4.0-Gbit/s serial link transceiver with data recovery using oversampling.

Chih-Kong Ken Yang, Ramin Farjad-Rad, Mark A. Horowitz

IEEE J. Solid State Circuits, 1998