Hiroaki Yoda

According to our database, Hiroaki Yoda authored at least 8 papers between 2003 and 2018.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2018

High-Speed Voltage Control Spintronics Memory (VoCSM) Having Broad Design Windows.

Naoharu Shimomura, Hiroaki Yoda, Tomoaki Inokuchi, Katsuhiko Koi, Hideyuki Sugiyama, Yushi Kato, Yuichi Ohsawa, Altansargai Buyandalai, Satoshi Shirotori, Soichi Oikawa, Mariko Shimizu, Mizue Ishikawa, Tiwari Ajay, Atsushi Kurobe

Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

2017

High-speed voltage-control spintronics memory focused on reduction in write current.

Hideyuki Sugiyama, Hiroaki Yoda, Katsuhiko Koi, Soichi Oikawa, Buyandalai Altansargai, Tomoaki Inokuchi, Satoshi Shirotori, Mariko Shimizu, Yuichi Kato, Yuichi Ohsawa, Mizue Ishikawa, Ajay Tiwari, Naoharu Shimomura, Yoshiaki Saito, Atsushi Kurobe

Proceedings of the 17th Non-Volatile Memory Technology Symposium, 2017

2016

High-Speed Magnetoresistive Random-Access Memory Random Number Generator Using Error-Correcting Code.

Tetsufumi Tanamoto, Naoharu Shimomura, Sumio Ikegawa, Mari Matsumoto, Shinobu Fujita, Hiroaki Yoda

CoRR, 2016

2015

The progresses of MRAM as a memory to save energy consumption and its potential for further reduction.

Hiroaki Yoda, E. Kitagawa, Naoharu Shimomura, S. Fujita, Minoru Amano

Proceedings of the Symposium on VLSI Circuits, 2015

2010

A 64Mb MRAM with clamped-reference and adequate-reference schemes.

Kenji Tsuchida, Tsuneo Inaba, Katsuyuki Fujita, Yoshihiro Ueda, Takafumi Shimizu, Yoshiaki Asao, Takeshi Kajiyama, Masayoshi Iwayama, Kuniaki Sugiura, Sumio Ikegawa, Tatsuya Kishi, Tadashi Kai, Minoru Amano, Naoharu Shimomura, Hiroaki Yoda, Yohji Watanabe

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2008

A Statistical Model for Assessing the Fault Tolerance of Variable Switching Currents for a 1Gb Spin Transfer Torque Magnetoresistive Random Access Memory.

Yoshiaki Asao, Masayoshi Iwayama, Kenji Tsuchida, Akihiro Nitayama, Hiroaki Yoda, Hisanori Aikawa, Sumio Ikegawa, Tatsuya Kishi

Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

2006

A 16Mb MRAM with FORK Wiring Scheme and Burst Modes.

Yoshihisa Iwata, Kenji Tsuchida, Tsuneo Inaba, Yui Shimizu, R. Takizawa, Yoshihiro Ueda, Tadahiko Sugibayashi, Yoshiaki Asao, Takeshi Kajiyama, Keiji Hosotani, Sumio Ikegawa, Tadashi Kai, M. Nakayama, Shuichi Tahara, Hiroaki Yoda

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2003

Resistance ratio read (R³) architecture for a burst operated 1.5V MRAM macro.

Tsuneo Inaba, Kenji Tsuchida, Tadahiko Sugibayashi, Shuichi Tahara, Hiroaki Yoda

Proceedings of the IEEE Custom Integrated Circuits Conference, 2003