Shinobu Fujita

According to our database, Shinobu Fujita authored at least 36 papers between 2004 and 2019.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2019

Circuit And Systems Based on Advanced MRAM for Near Future Computing Applications.

Shinobu Fujita, Satoshi Takaya, Susumu Takeda, Kazutaka Ikegami

Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

2017

Physically Unclonable Function Using an Initial Waveform of Ring Oscillators.

Tetsufumi Tanamoto, Shinichi Yasuda, Satoshi Takaya, Shinobu Fujita

IEEE Trans. Circuits Syst. II Express Briefs, 2017

Physically unclonable function using initial waveform of ring oscillators on 65 nm CMOS technology.

Tetsufumi Tanamoto, Satoshi Takaya, Nobuaki Sakamoto, Hirotsugu Kasho, Shinichi Yasuda, Takao Marukame, Shinobu Fujita, Yuichiro Mitani

CoRR, 2017

Novel memory hierarchy with e-STT-MRAM for near-future applications.

Shinobu Fujita, Hiroki Noguchi, Kazutaka Ikegami, Susumu Takeda, Kumiko Nomura, Keiko Abe

Proceedings of the 2017 International Symposium on VLSI Design, Automation and Test, 2017

2016

Physically Unclonable Function using Initial Waveform of Ring Oscillators.

Tetsufumi Tanamoto, Shinichi Yasuda, Satoshi Takaya, Shinobu Fujita

CoRR, 2016

High-Speed Magnetoresistive Random-Access Memory Random Number Generator Using Error-Correcting Code.

Tetsufumi Tanamoto, Naoharu Shimomura, Sumio Ikegawa, Mari Matsumoto, Shinobu Fujita, Hiroaki Yoda

CoRR, 2016

7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme.

Hiroki Noguchi, Kazutaka Ikegami, Satoshi Takaya, Eishi Arima, Keiichi Kushida, Atsushi Kawasumi, Hiroyuki Hara, Keiko Abe, Naoharu Shimomura, Junichi Ito, Shinobu Fujita, Takashi Nakada, Hiroshi Nakamura

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015

7.5 A 3.3ns-access-time 71.2μW/MHz 1Mb embedded STT-MRAM using physically eliminated read-disturb scheme and normally-off memory architecture.

Hiroki Noguchi, Kazutaka Ikegami, Keiichi Kushida, Keiko Abe, Shogo Itai, Satoshi Takaya, Naoharu Shimomura, Junichi Ito, Atsushi Kawasumi, Hiroyuki Hara, Shinobu Fujita

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

Immediate sleep: Reducing energy impact of peripheral circuits in STT-MRAM caches.

Eishi Arima, Hiroki Noguchi, Takashi Nakada, Shinobu Miwa, Susumu Takeda, Shinobu Fujita, Hiroshi Nakamura

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

2014

Highly reliable and low-power nonvolatile cache memory with advanced perpendicular STT-MRAM for high-performance CPU.

Hiroki Noguchi, Kazutaka Ikegami, Naoharu Shimomura, Tetsufumi Tanamoto, Junichi Ito, Shinobu Fujita

Proceedings of the Symposium on VLSI Circuits, 2014

Novel STT-MRAM-based last level caches for high performance processors using normally-off architectures.

Shinobu Fujita, Hiroki Noguchi, Kazutaka Ikegami, Susumu Takeda, Kumiko Nomura, Keiko Abe

Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

Novel nonvolatile memory hierarchies to realize "normally-off mobile processors".

Shinobu Fujita, Kumiko Nomura, Hiroki Noguchi, Susumu Takeda, Keiko Abe

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013

Patient Context: A New Concept for Gap Model to Understand Patient Satisfaction.

Shinobu Fujita, Kazuyoshi Hidaka

Proceedings of the Serviceology for Services, 2013

D-MRAM cache: enhancing energy efficiency with 3T-1MTJ DRAM/MRAM hybrid memory.

Hiroki Noguchi, Kumiko Nomura, Keiko Abe, Shinobu Fujita, Eishi Arima, Kyundong Kim, Takashi Nakada, Shinobu Miwa, Hiroshi Nakamura

Proceedings of the Design, Automation and Test in Europe, 2013

2012

Designing Nonvolatile Reconfigurable Switch-based FPGA through Overall Circuit Performance Evaluation.

Kazutaka Ikegami, Keiko Abe, Kumiko Nomura, Shinichi Yasuda, Masato Oda, Shinobu Fujita

Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

2011

Characterization and Implementation of Fault-Tolerant Vertical Links for 3-D Networks-on-Chip.

Igor Loi, Federico Angiolini, Shinobu Fujita, Subhasish Mitra, Luca Benini

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

2010

Performance analysis of 3D-IC for multi-core processors in sub-65nm CMOS technologies.

Kumiko Nomura, Keiko Abe, Shinobu Fujita, Yasuhiko Kurosawa, Atsushi Kageshima

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

High-performance FPGA based on novel DSS-MOSFET and non-volatile configuration memory (abstract only).

Shinichi Yasuda, Tetsufumi Tanamoto, Kazutaka Ikegami, Atsuhiro Kinoshita, Keiko Abe, Hirotaka Nishino, Shinobu Fujita

Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

Detachable nano-carbon chip with ultra low power.

Shinobu Fujita, Shinichi Yasuda, Daesung Lee, Xiangyu Chen, Deji Akinwande, H.-S. Philip Wong

Proceedings of the 47th Design Automation Conference, 2010

2009

ROM-Based Logic (RBL) Design: A Low-Power 16 Bit Multiplier.

Bipul C. Paul, Shinobu Fujita, Masaki Okajima

IEEE J. Solid State Circuits, 2009

Perspectives and Issues in 3D-IC from Designers' Point of View.

Shinobu Fujita, Keiko Abe, Kumiko Nomura, Shinichi Yasuda, Tetsufumi Tanamoto

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

CMOS vs Nano: comrades or rivals?

Deming Chen, Russell Tessier, Kaustav Banerjee, Mojy C. Chian, André DeHon, Shinobu Fujita, James Hutchby, Steve Trimberger

Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

Nano-electronics challenge chip designers meet real nano-electronics in 2010s?

Shinobu Fujita

Proceedings of the Design, Automation and Test in Europe, 2009

2008

1200μm² Physical Random-Number Generators Based on SiN MOSFET for Secure Smart-Card Application.

Mari Matsumoto, Shinichi Yasuda, Ryuji Ohba, Kazutaka Ikegami, Tetsufumi Tanamoto, Shinobu Fujita

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

ROM based logic (RBL) design: High-performance and low-power adders.

Bipul Chandra Paul, Shinobu Fujita, Masaki Okajima

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A low-overhead fault tolerance scheme for TSV-based 3D network on chip links.

Igor Loi, Subhasish Mitra, Thomas H. Lee, Shinobu Fujita, Luca Benini

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

2007

3-D Nanoarchitectures With Carbon Nanotube Mechanical Switches for Future On-Chip Network Beyond CMOS Architecture.

Shinobu Fujita, Kumiko Nomura, Keiko Abe, Thomas H. Lee

IEEE Trans. Circuits Syst. I Regul. Pap., 2007

Prospect of ballistic CNFET in high performance applications: Modeling and analysis.

Bipul C. Paul, Shinobu Fujita, Masaki Okajima, Thomas Lee

ACM J. Emerg. Technol. Comput. Syst., 2007

ProBoPortable: does the cellular phone software promote emergent division of labor in project-based learning?

Toshio Mochizuki, Hiroshi Kato, Kazaru Yaegashi, Toshihisa Nishimori, Yusuke Nagamori, Shinobu Fujita

Proceedings of the 7th Iternational Conference on Computer Supported Collaborative Learning, 2007

Compact Fault Recovering Flip-Flop with Adjusting Clock Timing Triggered by Error Detection.

Shinichi Yasuda, Shinobu Fujita

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006

Novel Design of Three-Dimensional Crossbar for Future Network on Chip based on Post-Silicon Devices.

Kumiko Nomura, Keiko Abe, Shinobu Fujita, André DeHon

Proceedings of the 1st International ICST Conference on Nano-Networks, 2006

3D on-chip networking technology based on post-silicon devices for future networks-on-chip.

Shinobu Fujita, Kumiko Nomura, Keiko Abe, Thomas H. Lee

Proceedings of the 1st International ICST Conference on Nano-Networks, 2006

Si Nanocrystal MOSFET with Silicon Nitride Tunnel Insulator for High-rate Random Number Generation.

Ryuji Ohba, Daisuke Matsushita, Koichi Muraoka, Shinichi Yasuda, Tetsufumi Tanamoto, Ken Uchida, Shinobu Fujita

Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

Modeling and analysis of circuit performance of ballistic CNFET.

Bipul C. Paul, Shinobu Fujita, Masaki Okajima, Thomas Lee

Proceedings of the 43rd Design Automation Conference, 2006

2005

Physical random number generators for cryptographic application in mobile devices.

Shinichi Yasuda, Tetsufumi Tanamoto, Ryuji Ohba, Keiko Abe, Hanae Nozaki, Shinobu Fujita

Proceedings of the 31st European Solid-State Circuits Conference, 2005

2004

Physical random number generator based on MOS structure after soft breakdown.

Shinichi Yasuda, Hideki Satake, Tetsufumi Tanamoto, Ryuji Ohba, Ken Uchida, Shinobu Fujita

IEEE J. Solid State Circuits, 2004