Shinobu Fujita

According to our database1, Shinobu Fujita authored at least 36 papers between 2004 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.



In proceedings 
PhD thesis 




Circuit And Systems Based on Advanced MRAM for Near Future Computing Applications.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

Physically Unclonable Function Using an Initial Waveform of Ring Oscillators.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

Physically unclonable function using initial waveform of ring oscillators on 65 nm CMOS technology.
CoRR, 2017

Novel memory hierarchy with e-STT-MRAM for near-future applications.
Proceedings of the 2017 International Symposium on VLSI Design, Automation and Test, 2017

Physically Unclonable Function using Initial Waveform of Ring Oscillators.
CoRR, 2016

High-Speed Magnetoresistive Random-Access Memory Random Number Generator Using Error-Correcting Code.
CoRR, 2016

7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

7.5 A 3.3ns-access-time 71.2μW/MHz 1Mb embedded STT-MRAM using physically eliminated read-disturb scheme and normally-off memory architecture.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

Immediate sleep: Reducing energy impact of peripheral circuits in STT-MRAM caches.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Highly reliable and low-power nonvolatile cache memory with advanced perpendicular STT-MRAM for high-performance CPU.
Proceedings of the Symposium on VLSI Circuits, 2014

Novel STT-MRAM-based last level caches for high performance processors using normally-off architectures.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

Novel nonvolatile memory hierarchies to realize "normally-off mobile processors".
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

Patient Context: A New Concept for Gap Model to Understand Patient Satisfaction.
Proceedings of the Serviceology for Services, 2013

D-MRAM cache: enhancing energy efficiency with 3T-1MTJ DRAM/MRAM hybrid memory.
Proceedings of the Design, Automation and Test in Europe, 2013

Designing Nonvolatile Reconfigurable Switch-based FPGA through Overall Circuit Performance Evaluation.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

Characterization and Implementation of Fault-Tolerant Vertical Links for 3-D Networks-on-Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Performance analysis of 3D-IC for multi-core processors in sub-65nm CMOS technologies.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

High-performance FPGA based on novel DSS-MOSFET and non-volatile configuration memory (abstract only).
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

Detachable nano-carbon chip with ultra low power.
Proceedings of the 47th Design Automation Conference, 2010

ROM-Based Logic (RBL) Design: A Low-Power 16 Bit Multiplier.
IEEE J. Solid State Circuits, 2009

Perspectives and Issues in 3D-IC from Designers' Point of View.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

CMOS vs Nano: comrades or rivals?
Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

Nano-electronics challenge chip designers meet real nano-electronics in 2010s?
Proceedings of the Design, Automation and Test in Europe, 2009

1200μm<sup>2</sup> Physical Random-Number Generators Based on SiN MOSFET for Secure Smart-Card Application.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

ROM based logic (RBL) design: High-performance and low-power adders.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A low-overhead fault tolerance scheme for TSV-based 3D network on chip links.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

3-D Nanoarchitectures With Carbon Nanotube Mechanical Switches for Future On-Chip Network Beyond CMOS Architecture.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007

Prospect of ballistic CNFET in high performance applications: Modeling and analysis.
ACM J. Emerg. Technol. Comput. Syst., 2007

ProBoPortable: does the cellular phone software promote emergent division of labor in project-based learning?
Proceedings of the 7th Iternational Conference on Computer Supported Collaborative Learning, 2007

Compact Fault Recovering Flip-Flop with Adjusting Clock Timing Triggered by Error Detection.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

Novel Design of Three-Dimensional Crossbar for Future Network on Chip based on Post-Silicon Devices.
Proceedings of the 1st International ICST Conference on Nano-Networks, 2006

3D on-chip networking technology based on post-silicon devices for future networks-on-chip.
Proceedings of the 1st International ICST Conference on Nano-Networks, 2006

Si Nanocrystal MOSFET with Silicon Nitride Tunnel Insulator for High-rate Random Number Generation.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

Modeling and analysis of circuit performance of ballistic CNFET.
Proceedings of the 43rd Design Automation Conference, 2006

Physical random number generators for cryptographic application in mobile devices.
Proceedings of the 31st European Solid-State Circuits Conference, 2005

Physical random number generator based on MOS structure after soft breakdown.
IEEE J. Solid State Circuits, 2004