Shuichi Tahara

According to our database, Shuichi Tahara authored at least 7 papers between 2003 and 2007.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2007

A 16-Mb Toggle MRAM With Burst Modes.

Tadahiko Sugibayashi, Noboru Sakimura, Takeshi Honda, Kiyokazu Nagahara, Kiyotaka Tsuji, Hideaki Numata, Sadahiko Miura, Ken-ichi Shimura, Yuko Kato, Shinsaku Saito, Yoshiyuki Fukumoto, Hiroaki Honjo, Tetsuhiro Suzuki, Katsumi Suemitsu, Tomonori Mukai, Kaoru Mori, Ryusuke Nebashi, Shunsuke Fukami, Norikazu Ohshima, Hiromitsu Hada, Nobuyuki Ishiwata, Naoki Kasai, Shuichi Tahara

IEEE J. Solid State Circuits, 2007

MRAM Cell Technology for Over 500-MHz SoC.

Noboru Sakimura, Tadahiko Sugibayashi, Takeshi Honda, Hiroaki Honjo, Shinsaku Saito, Tetsuhiro Suzuki, Nobuyuki Ishiwata, Shuichi Tahara

IEEE J. Solid State Circuits, 2007

MRAM Applications Using Unlimited Write Endurance.

Tadahiko Sugibayashi, Takeshi Honda, Noboru Sakimura, Shuichi Tahara, Naoki Kasai

IEICE Trans. Electron., 2007

Writing Circuitry for Toggle MRAM to Screen Intermittent Failure Mode.

Takeshi Honda, Noboru Sakimura, Tadahiko Sugibayashi, Naoki Kasai, Hiromitsu Hada, Shuichi Tahara

IEICE Trans. Electron., 2007

TD: Emerging Devices Devices and Circuits.

Eugenio Cantatore, Shuichi Tahara

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2006

A 16Mb MRAM with FORK Wiring Scheme and Burst Modes.

Yoshihisa Iwata, Kenji Tsuchida, Tsuneo Inaba, Yui Shimizu, R. Takizawa, Yoshihiro Ueda, Tadahiko Sugibayashi, Yoshiaki Asao, Takeshi Kajiyama, Keiji Hosotani, Sumio Ikegawa, Tadashi Kai, M. Nakayama, Shuichi Tahara, Hiroaki Yoda

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2003

Resistance ratio read (R³) architecture for a burst operated 1.5V MRAM macro.

Tsuneo Inaba, Kenji Tsuchida, Tadahiko Sugibayashi, Shuichi Tahara, Hiroaki Yoda

Proceedings of the IEEE Custom Integrated Circuits Conference, 2003