Hiroshi Inokawa

According to our database, Hiroshi Inokawa authored at least 19 papers between 1997 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

Multiple Quantum Barrier Avalanche Photodiode Based on GaN/AlGaN Heterostructures for Long Wavelength Infrared Detection.

Somrita Ghosh, Aritra Acharyya, Arindam Biswas, Amit Banerjee, Hiroshi Inokawa, Hiroaki Satoh, Alexey Y. Seteikin, I. G. Samusev

IEEE Access, 2024

2023

Refractive Index Measurement Using SOI Photodiode with SP Antenna toward SOI CMOS-Compatible Integrated Optical Biosensor.

Hiroaki Satoh, Koki Isogai, Shohei Iwata, Taiki Aso, Ryosuke Hayashi, Shu Takeuchi, Hiroshi Inokawa

Sensors, January, 2023

Folded-Dipole Antenna Geometrical Analysis for THz Microbolometer.

Arie Pangesti Aji, Hiroaki Satoh, Catur Apriono, Eko Tjipto Rahardjo, Hiroshi Inokawa

IEEE Access, 2023

2022

Responsivity and NEP Improvement of Terahertz Microbolometer by High-Impedance Antenna.

Arie Pangesti Aji, Hiroaki Satoh, Catur Apriono, Eko Tjipto Rahardjo, Hiroshi Inokawa

Sensors, 2022

Angle-sensitive pixel based on silicon-on-insulator p-n junction photodiode with aluminum grating gate electrode.

Hiroaki Satoh, Ken Kawakubo, Atsushi Ono, Hiroshi Inokawa

IEICE Electron. Express, 2022

2020

Angle-Sensitive Detector Based on Silicon-On-Insulator Photodiode Stacked with Surface Plasmon Antenna.

Anitharaj Nagarajan, Shusuke Hara, Hiroaki Satoh, Aruna Priya Panchanathan, Hiroshi Inokawa

Sensors, 2020

Angular selectivity of SOI photodiode with surface plasmon antenna.

Anitharaj Nagarajan, Shusuke Hara, Hiroaki Satoh, Aruna Priya Panchanathan, Hiroshi Inokawa

IEICE Electron. Express, 2020

2018

Application of bow-tie surface plasmon antenna to silicon on insulator nanowire photodiode for enhanced light absorption.

Yash Sharma, Hiroaki Satoh, Hiroshi Inokawa

IEICE Electron. Express, 2018

2016

Evaluation of multidrug cancer chronotherapy based on cell cycle model under influences of circadian clock.

Hiroshi Inokawa, Norihiro Katayama, Mitsuyuki Nakao

Proceedings of the 38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2016

2012

Effect of Arrangement of Input Gates on Logic Switching Characteristics of Nanodot Array Device.

Mingu Jo, Yuki Kato, Masashi Arita, Yukinori Ono, Akira Fujiwara, Hiroshi Inokawa, Yasuo Takahashi, Jung-Bum Choi

IEICE Trans. Electron., 2012

2009

Full Adder Operation Based on Si Nanodot Array Device with Multiple Inputs and Outputs.

Takuya Kaizawa, Mingyu Jo, Masashi Arita, Akira Fujiwara, Kenji Yamazaki, Yukinori Ono, Hiroshi Inokawa, Yasuo Takahashi

Int. J. Nanotechnol. Mol. Comput., 2009

2007

Design of a Two-Bit-Per-Cell Content-Addressable Memory Using Single-Electron Transistors.

Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi, Hiroshi Inokawa, Yasuo Takahashi

J. Multiple Valued Log. Soft Comput., 2007

Transfer and Detection of Single Electrons Using Metal-Oxide-Semiconductor Field-Effect Transistors.

Wancheng Zhang, Katsuhiko Nishiguchi, Yukinori Ono, Akira Fujiwara, Hiroshi Yamaguchi, Hiroshi Inokawa, Yasuo Takahashi, Nan-Jian Wu

IEICE Trans. Electron., 2007

2006

A High-Density Ternary Content-Addressable Memory Using Single-Electron Transistors.

Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi, Hiroshi Inokawa, Katsuhiko Nishiguchi, Yasuo Takahashi

Proceedings of the 36th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2006), 2006

2005

A Two-Bit-per-Cell Content-Addressable Memory Using Single-Electron Transistors.

Katsuhiko Degawa, Takafumi Aoki, Hiroshi Inokawa, Tatsuo Higuchi, Yasuo Takahashi

Proceedings of the 35th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2005), 2005

2004

A Single-Electron-Transistor Logic Gate Family and Its Application - Part II: Design and Simulation of a 7-3 Parallel Counter with Linear Summation and Multiple-Valued Latch Functions.

Hiroshi Inokawa, Yasuo Takahashi, Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi

Proceedings of the 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 2004

A Single-Electron-Transistor Logic Gate Family and Its Application - Part I: Basic Components for Binary, Multiple-Valued and Mixed-Mode Logic.

Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi, Hiroshi Inokawa, Yasuo Takahashi

Proceedings of the 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 2004

2003

Experimental and Simulation Studies of Single-Electron-Transistor-Based Multiple-Valued Logic.

Hiroshi Inokawa, Yasuo Takahashi

Proceedings of the 33rd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2003), 2003

1997

A 0.5-V MTCMOS/SIMOX logic gate.

Takakuni Douseki, Satoshi Shigematsu, Junzo Yamada, Mitsuru Harada, Hiroshi Inokawa, Toshiaki Tsuchiya

IEEE J. Solid State Circuits, 1997