Yasuo Takahashi

According to our database, Yasuo Takahashi authored at least 13 papers between 2000 and 2017.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2017

Associative search using pseudo-analog memristors.

Mika Laiho, Mika Grönroos, Jussi H. Poikonen, Eero Lehtonen, Reon Katsumura, Atsushi T.-Fukuchi, Masashi Arita, Yasuo Takahashi

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016

Brownian Circuits: Designs.

Jia Lee, Ferdinand Peper, Sorin Dan Cotofana, Makoto Naruse, Motoichi Ohtsu, Tadashi Kawazoe, Yasuo Takahashi, Tetsuya Shimokawa, Laszlo B. Kish, Tohru Kubota

Int. J. Unconv. Comput., 2016

2012

Effect of Arrangement of Input Gates on Logic Switching Characteristics of Nanodot Array Device.

Mingu Jo, Yuki Kato, Masashi Arita, Yukinori Ono, Akira Fujiwara, Hiroshi Inokawa, Yasuo Takahashi, Jung-Bum Choi

IEICE Trans. Electron., 2012

2011

Anomalous microstructure formed at the interface between copper ribbon and tin-deposited copper plate by ultrasonic bonding.

Masakatsu Maeda, Takaaki Sato, Naoto Inoue, Daisuke Yagi, Yasuo Takahashi

Microelectron. Reliab., 2011

2009

Full Adder Operation Based on Si Nanodot Array Device with Multiple Inputs and Outputs.

Takuya Kaizawa, Mingyu Jo, Masashi Arita, Akira Fujiwara, Kenji Yamazaki, Yukinori Ono, Hiroshi Inokawa, Yasuo Takahashi

Int. J. Nanotechnol. Mol. Comput., 2009

2007

Design of a Two-Bit-Per-Cell Content-Addressable Memory Using Single-Electron Transistors.

Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi, Hiroshi Inokawa, Yasuo Takahashi

J. Multiple Valued Log. Soft Comput., 2007

Transfer and Detection of Single Electrons Using Metal-Oxide-Semiconductor Field-Effect Transistors.

Wancheng Zhang, Katsuhiko Nishiguchi, Yukinori Ono, Akira Fujiwara, Hiroshi Yamaguchi, Hiroshi Inokawa, Yasuo Takahashi, Nan-Jian Wu

IEICE Trans. Electron., 2007

2006

A High-Density Ternary Content-Addressable Memory Using Single-Electron Transistors.

Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi, Hiroshi Inokawa, Katsuhiko Nishiguchi, Yasuo Takahashi

Proceedings of the 36th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2006), 2006

2005

A Two-Bit-per-Cell Content-Addressable Memory Using Single-Electron Transistors.

Katsuhiko Degawa, Takafumi Aoki, Hiroshi Inokawa, Tatsuo Higuchi, Yasuo Takahashi

Proceedings of the 35th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2005), 2005

2004

A Single-Electron-Transistor Logic Gate Family and Its Application - Part II: Design and Simulation of a 7-3 Parallel Counter with Linear Summation and Multiple-Valued Latch Functions.

Hiroshi Inokawa, Yasuo Takahashi, Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi

Proceedings of the 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 2004

A Single-Electron-Transistor Logic Gate Family and Its Application - Part I: Basic Components for Binary, Multiple-Valued and Mixed-Mode Logic.

Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi, Hiroshi Inokawa, Yasuo Takahashi

Proceedings of the 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 2004

2003

Experimental and Simulation Studies of Single-Electron-Transistor-Based Multiple-Valued Logic.

Hiroshi Inokawa, Yasuo Takahashi

Proceedings of the 33rd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2003), 2003

2000

Silicon Single-Electron Devices and Their Applications.

Yasuo Takahashi, Akira Fujiwara, Yukinori Ono, Katsumi Murase

Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic, 2000