Junzo Yamada

According to our database, Junzo Yamada authored at least 6 papers between 1994 and 2000.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2000

2-GHz RF front-end circuits in CMOS/SIMOX operating at an extremely low voltage of 0.5 V.

Mitsuru Harada, Tsuneo Tsukahara, Junichi Kodate, Akihiro Yamagishi, Junzo Yamada

IEEE J. Solid State Circuits, 2000

1997

A 1-V high-speed MTCMOS circuit scheme for power-down application circuits.

Satoshi Shigematsu, Shin'ichiro Mutoh, Yasuyuki Matsuya, Yasuyuki Tanabe, Junzo Yamada

IEEE J. Solid State Circuits, 1997

A 0.5-V MTCMOS/SIMOX logic gate.

Takakuni Douseki, Satoshi Shigematsu, Junzo Yamada, Mitsuru Harada, Hiroshi Inokawa, Toshiaki Tsuchiya

IEEE J. Solid State Circuits, 1997

1996

A 1-V multithreshold-voltage CMOS digital signal processor for mobile phone application.

Shinichiro Mutoh, Satoshi Shigematsu, Yasuyuki Matsuya, H. Fukuda, T. Kaneko, Junzo Yamada

IEEE J. Solid State Circuits, 1996

1995

1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS.

Shin'ichiro Mutoh, Takakuni Douseki, Yasuyuki Matsuya, Takahko Aoki, Satoshi Shigematsu, Junzo Yamada

IEEE J. Solid State Circuits, August, 1995

1994

1 V power supply, low-power consumption A/D conversion technique with swing-suppression noise shaping.

Yasuyuki Matsuya, Junzo Yamada

IEEE J. Solid State Circuits, December, 1994