Hiroyuki Akasaka

According to our database, Hiroyuki Akasaka authored at least 3 papers between 2012 and 2014.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2014

Energy-efficient High-level Synthesis for HDR Architecture with Multi-stage Clock Gating.

Hiroyuki Akasaka, Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa

IPSJ Trans. Syst. LSI Des. Methodol., 2014

2013

Energy-efficient High-level Synthesis for HDR Architectures with Clock Gating Based on Concurrency-oriented Scheduling.

Hiroyuki Akasaka, Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa

IPSJ Trans. Syst. LSI Des. Methodol., 2013

2012

Energy-efficient high-level synthesis for HDR architectures with clock gating.

Hiroyuki Akasaka, Masao Yanagisawa, Nozomu Togawa

Proceedings of the International SoC Design Conference, 2012