Nozomu Togawa
Orcid: 0000-0003-3400-3587
According to our database1,
Nozomu Togawa
authored at least 295 papers
between 1994 and 2024.
Collaborative distances:
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Bibliography
2024
Hardware-Trojan Detection at Gate-Level Netlists Using a Gradient Boosting Decision Tree Model and Its Extension Using Trojan Probability Propagation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., January, 2024
Giving a Quasi-Initial Solution to Ising Machines by Controlling External Magnetic Field Coefficients.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., January, 2024
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., January, 2024
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., January, 2024
Toward Practical Benchmarks of Ising Machines: A Case Study on the Quadratic Knapsack Problem.
CoRR, 2024
A GPU-Based Ising Machine With a Multi-Spin-Flip Capability for Constrained Combinatorial Optimization.
IEEE Access, 2024
Proceedings of the IEEE International Conference on Consumer Electronics, 2024
Time-Dependent Multi-Objective Trip Planning by Ant Colony Optimization with Route API.
Proceedings of the IEEE International Conference on Consumer Electronics, 2024
Evaluation of Ensemble Learning Models for Hardware-Trojan Identification at Gate-level Netlists.
Proceedings of the IEEE International Conference on Consumer Electronics, 2024
An Interaction Coefficient Control Method for Setting Initial Solutions to Ising Machines.
Proceedings of the IEEE International Conference on Consumer Electronics, 2024
Proceedings of the IEEE International Conference on Consumer Electronics, 2024
Proceedings of the IEEE International Conference on Consumer Electronics, 2024
Proceedings of the IEEE International Conference on Consumer Electronics, 2024
2023
Spin-Variable Reduction Method for Handling Linear Equality Constraints in Ising Machines.
IEEE Trans. Computers, August, 2023
IEICE Trans. Inf. Syst., April, 2023
IEEE Trans. Computers, February, 2023
CoRR, 2023
IEEE Access, 2023
IEEE Access, 2023
Proceedings of the 36th IEEE International System-on-Chip Conference, 2023
Proceedings of the 25th IEEE International Conference on Intelligent Transportation Systems, 2023
Proceedings of the IEEE International Conference on Consumer Electronics, 2023
Proceedings of the IEEE International Conference on Consumer Electronics, 2023
A Quasi-Initial Solution Giving Method for Ising Machines by Controlling External Magnetic Field Coefficients.
Proceedings of the IEEE International Conference on Consumer Electronics, 2023
Proceedings of the IEEE International Conference on Consumer Electronics, 2023
2022
IEEE Trans. Computers, 2022
Hybrid Annealing Method Based on subQUBO Model Extraction With Multiple Solution Instances.
IEEE Trans. Computers, 2022
Carrying-mode Free Indoor Positioning Using Smartphone and Smartwatch and Its Evaluations.
J. Inf. Process., 2022
Hardware-Trojan Detection Based on the Structural Features of Trojan Circuits Using Random Forests.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2022
Multi-Objective Trip Planning Based on Ant Colony Optimization Utilizing Trip Records.
IEEE Access, 2022
Proceedings of the 35th IEEE International System-on-Chip Conference, 2022
Effective Hardware-Trojan Feature Extraction Against Adversarial Attacks at Gate-Level Netlists.
Proceedings of the 28th IEEE International Symposium on On-Line Testing and Robust System Design, 2022
An Anomalous Behavior Detection Method for IoT Devices Based on Power Waveform Shapes.
Proceedings of the 28th IEEE International Symposium on On-Line Testing and Robust System Design, 2022
Proceedings of the IEEE International Conference on Consumer Electronics, 2022
Proceedings of the IEEE International Conference on Consumer Electronics, 2022
A PDR Method Using Smartglasses Reducing Accumulated Errors by Detecting User's Stop Motions.
Proceedings of the IEEE International Conference on Consumer Electronics, 2022
Hardware-Trojan Detection at Gate-level Netlists using Gradient Boosting Decision Tree Models.
Proceedings of the 12th IEEE International Conference on Consumer Electronics, 2022
Proceedings of the International Conference on Field-Programmable Technology, 2022
2021
Generating Adversarial Examples for Hardware-Trojan Detection at Gate-Level Netlists.
J. Inf. Process., 2021
A Route Recommendation Method Considering Individual User's Preferences by Monte-Carlo Tree Search and Its Evaluations.
J. Inf. Process., 2021
IPSJ Trans. Syst. LSI Des. Methodol., 2021
Mapping Induced Subgraph Isomorphism Problems to Ising Models and Its Evaluations by an Ising Machine.
IEICE Trans. Inf. Syst., 2021
An Ising Machine-Based Solver for Visiting-Route Recommendation Problems in Amusement Parks.
IEICE Trans. Inf. Syst., 2021
Solving Constrained Slot Placement Problems Using an Ising Machine and Its Evaluations.
IEICE Trans. Inf. Syst., 2021
An Anomalous Behavior Detection Method Utilizing Extracted Application-Specific Power Behaviors.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2021
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2021
A Two-Stage Hardware Trojan Detection Method Considering the Trojan Probability of Neighbor Nets.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2021
IEEE Access, 2021
A Three-Stage Annealing Method Solving Slot-Placement Problems Using an Ising Machine.
IEEE Access, 2021
An Approach to the Vehicle Routing Problem with Balanced Pick-up Using Ising Machines.
Proceedings of the International Symposium on VLSI Design, Automation and Test, 2021
Proceedings of the 24th IEEE International Intelligent Transportation Systems Conference, 2021
An Anomalous Behavior Detection Method Based on Power Analysis Utilizing Steady State Power Waveform Predicted by LSTM.
Proceedings of the 27th IEEE International Symposium on On-Line Testing and Robust System Design, 2021
Hardware-Trojan Classification based on the Structure of Trigger Circuits Utilizing Random Forests.
Proceedings of the 27th IEEE International Symposium on On-Line Testing and Robust System Design, 2021
Data Augmentation for Machine Learning-Based Hardware Trojan Detection at Gate-Level Netlists.
Proceedings of the 27th IEEE International Symposium on On-Line Testing and Robust System Design, 2021
An Indoor Positioning Method using Smartphone and Smartwatch Independent of Carrying Modes.
Proceedings of the IEEE International Conference on Consumer Electronics, 2021
Visiting-Route Recommendation in Amusement Parks and its Evaluations by an Ising Machine.
Proceedings of the IEEE International Conference on Consumer Electronics, 2021
Reducing Writing Energy Consumption for Non-Volatile Registers Utilizing Frequent Patterns of Sequential Bits on RISC-V Architecture.
Proceedings of the IEEE International Conference on Consumer Electronics, 2021
A PDR Method Combining Smartphone and Smartwatch based on Multi-Scenario Map Matching.
Proceedings of the 10th IEEE Global Conference on Consumer Electronics, 2021
Proceedings of the International Conference on Field-Programmable Technology, 2021
Toward Learning Robust Detectors from Imbalanced Datasets Leveraging Weighted Adversarial Training.
Proceedings of the Cryptology and Network Security - 20th International Conference, 2021
2020
Scalable Stochastic Number Duplicators for Accuracy-flexible Arithmetic Circuit Design.
IPSJ Trans. Syst. LSI Des. Methodol., 2020
Trojan-Net Classification for Gate-Level Hardware Design Utilizing Boundary Net Structures.
IEICE Trans. Inf. Syst., 2020
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2020
IEEE Access, 2020
Document-Level Sentiment Classification in Japanese by Stem-Based Segmentation with Category and Data-Source Information.
Proceedings of the IEEE 14th International Conference on Semantic Computing, 2020
Designing Stochastic Number Generators Sharing a Random Number Source based on the Randomization Function.
Proceedings of the 18th IEEE International New Circuits and Systems Conference, 2020
Multi-Resolutional Image Format Using Stochastic Numbers and Its Hardware Implementation.
Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems, 2020
An Anomalous Behavior Detection Method for IoT Devices by Extracting Application-Specific Power Behaviors.
Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020
Evaluation on Hardware-Trojan Detection at Gate-Level IP Cores Utilizing Machine Learning Methods.
Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020
Proceedings of the 2020 IEEE International Conference on Consumer Electronics (ICCE), 2020
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
2019
IPSJ Trans. Syst. LSI Des. Methodol., 2019
Bicycle Behavior Recognition Using 3-Axis Acceleration Sensor and 3-Axis Gyro Sensor Equipped with Smartphone.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019
A Fully-Connected Ising Model Embedding Method and Its Evaluation for CMOS Annealing Machines.
IEICE Trans. Inf. Syst., 2019
A Multiple Cyclic-Route Generation Method with Route Length Constraint Considering Point-of-Interests.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019
A Robust Indoor/Outdoor Detection Method Based on Spatial and Temporal Features of Sparse GPS Measured Positions.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019
Static Error Analysis and Optimization of Faithfully Truncated Adders for Area-Power Efficient FIR Designs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019
Empirical Evaluation on Anomaly Behavior Detection for Low-Cost Micro-Controllers Utilizing Accurate Power Analysis.
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019
Proceedings of the International Conference on Field-Programmable Technology, 2019
Error Correction System using Stochastic Numbers in Symmetric Channels and Z Channels.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
Proceedings of the IEEE International Conference on Consumer Electronics, 2019
Efficient Ising Model Mapping for Induced Subgraph Isomorphism Problems Using Ising Machines.
Proceedings of the 9th IEEE International Conference on Consumer Electronics, 2019
A Multiple Coefficients Trial Method to Solve Combinatorial Optimization Problems for Simulated-annealing-based Ising Machines.
Proceedings of the 9th IEEE International Conference on Consumer Electronics, 2019
Mapping Constrained Slot-Placement Problems to Ising Models and its Evaluations by an Ising Machine.
Proceedings of the 9th IEEE International Conference on Consumer Electronics, 2019
A Route Recommendation Method Based on Personal Preferences by Monte-Carlo Tree Search.
Proceedings of the 9th IEEE International Conference on Consumer Electronics, 2019
Proceedings of the Computer Security - ESORICS 2019 International Workshops, 2019
A Travel Decision Support Algorithm: Landmark Activity Extraction from Japanese Travel Comments.
Proceedings of the Computer and Information Science, 2019
2018
Scan-based Side-channel Attack against HMAC-SHA-256 Circuits Based on Isolating Bit-transition Groups Using Scan Signatures.
IPSJ Trans. Syst. LSI Des. Methodol., 2018
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018
Hardware Trojan Detection and Classification Based on Logic Testing Utilizing Steady State Learning.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018
A Stayed Location Estimation Method for Sparse GPS Positioning Information Based on Positioning Accuracy and Short-Time Cluster Removal.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018
Stochastic Number Duplicators Based on Bit Re-Arrangement Using Randomized Bit Streams.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018
Extension and Performance/Accuracy Formulation for Optimal GeAr-Based Approximate Adder Designs.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018
Empirical Evaluation and Optimization of Hardware-Trojan Classification for Gate-Level Netlists Based on Multi-Layer Neural Networks.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018
Proceedings of the 2018 International Symposium on VLSI Design, 2018
Proceedings of the 17th IEEE International Conference On Trust, 2018
Proceedings of the 2018 New Generation of CAS, 2018
A loop structure optimization targeting high-level synthesis of fast number theoretic transform.
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018
A Trojan-invalidating Circuit Based on Signal Transitions and Its FPGA Implementation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
An Effective Stochastic Number Duplicator and Its Evaluations Using Composite Arithmetic Circuits.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018
Detecting the Existence of Malfunctions in Microcontrollers Utilizing Power Analysis.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018
Proceedings of the IEEE International Conference on Consumer Electronics, 2018
Proceedings of the IEEE International Conference on Consumer Electronics, 2018
Proceedings of the 8th IEEE International Conference on Consumer Electronics - Berlin, 2018
Proceedings of the 8th IEEE International Conference on Consumer Electronics - Berlin, 2018
Proceedings of the 8th IEEE International Conference on Consumer Electronics - Berlin, 2018
Designing Subspecies of Hardware Trojans and Their Detection Using Neural Network Approach.
Proceedings of the 8th IEEE International Conference on Consumer Electronics - Berlin, 2018
Landmark Seasonal Travel Distribution and Activity Prediction Based on Language-specific Analysis.
Proceedings of the IEEE International Conference on Big Data (IEEE BigData 2018), 2018
Capacitance Measurement of Running Hardware Devices and its Application to Malicious Modification Detection.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018
2017
A Bitwidth-Aware High-Level Synthesis Algorithm Using Operation Chainings for Tiled-DR Architectures.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017
A Floorplan Aware High-Level Synthesis Algorithm with Body Biasing for Delay Variation Compensation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017
Trojan-Net Feature Extraction and Its Application to Hardware-Trojan Detection for Gate-Level Netlists Using Random Forest.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017
A Hardware-Trojan Classification Method Using Machine Learning at Gate-Level Netlists Based on Trojan Features.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017
A Safe and Comprehensive Route Finding Algorithm for Pedestrians Based on Lighting and Landmark Conditions.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017
Robust AES circuit design for delay variation using suspicious timing error prediction.
Proceedings of the International SoC Design Conference, 2017
Proceedings of the International SoC Design Conference, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Trojan-feature extraction at gate-level netlists and its application to hardware-Trojan detection using random forest classifier.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017
Hardware Trojans classification for gate-level netlists using multi-layer neural networks.
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017
Proceedings of the 7th IEEE International Conference on Consumer Electronics - Berlin, 2017
Proceedings of the 7th IEEE International Conference on Consumer Electronics - Berlin, 2017
An accurate indoor positioning algorithm using particle filter based on the proximity of bluetooth beacons.
Proceedings of the IEEE 6th Global Conference on Consumer Electronics, 2017
Proceedings of the IEEE 6th Global Conference on Consumer Electronics, 2017
Proceedings of the 12th IEEE International Conference on ASIC, 2017
Proceedings of the 12th IEEE International Conference on ASIC, 2017
Proceedings of the 12th IEEE International Conference on ASIC, 2017
Floorplan-driven high-level synthesis using volatile/non-volatile registers for hybrid energy-harvesting systems.
Proceedings of the 12th IEEE International Conference on ASIC, 2017
2016
Hardware-Trojans Rank: Quantitative Evaluation of Security Threats at Gate-Level Netlists by Pattern Matching.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016
A Bit-Write-Reducing and Error-Correcting Code Generation Method by Clustering ECC Codewords for Non-Volatile Memories.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016
A Highly-Adaptable and Small-Sized In-Field Power Analyzer for Low-Power IoT Devices.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016
A Multi-Scenario High-Level Synthesis Algorithm for Variation-Tolerant Floorplan-Driven Design.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016
Interconnection-Delay and Clock-Skew Estimate Modelings for Floorplan-Driven High-Level Synthesis Targeting FPGA Designs.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016
Multi-scenario high-level synthesis for dynamic delay variation and its evaluation on FPGA platforms.
IEICE Electron. Express, 2016
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016
A delay variation and floorplan aware high-level synthesis algorithm with body biasing.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016
Proceedings of the International SoC Design Conference, 2016
Proceedings of the International SoC Design Conference, 2016
Scalable and small-sized power analyzer design with signal-averaging noise reduction for low-power IoT devices.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016
Pedestrian navigation based on landmark recognition using glass-type wearable devices.
Proceedings of the IEEE 5th Global Conference on Consumer Electronics, 2016
Comprehensive deformed map generation for wristwatch-type wearable devices based on landmark-based partitioning.
Proceedings of the IEEE 5th Global Conference on Consumer Electronics, 2016
A safe and comprehensive route finding method for pedestrian based on lighting and landmark.
Proceedings of the IEEE 5th Global Conference on Consumer Electronics, 2016
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016
2015
An Effective Suspicious Timing-Error Prediction Circuit Insertion Algorithm Minimizing Area Overhead.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015
A High-Level Synthesis Algorithm with Inter-Island Distance Based Operation Chainings for RDR Architectures.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015
A Hardware-Trojans Identifying Method Based on Trojan Net Scoring at Gate-Level Netlists.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015
Code Generation Limiting Maximum and Minimum Hamming Distances for Non-Volatile Memories.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015
A Floorplan-Driven High-Level Synthesis Algorithm for Multiplexer Reduction Targeting FPGA Designs.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015
An Energy-Efficient Floorplan Driven High-Level Synthesis Algorithm for Multiple Clock Domains Design.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015
A process-variation-aware multi-scenario high-level synthesis algorithm for distributed-register architectures.
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015
A floorplan-driven high-level synthesis algorithm with multiple-operation chainings based on path enumeration.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Bit-Write-Reducing and Error-Correcting Code Generation by Clustering Error-Correcting Codewords for Non-Volatile Memories.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015
Proceedings of the 2015 IEEE Global Communications Conference, 2015
Proceedings of the IEEE 4th Global Conference on Consumer Electronics, 2015
Proceedings of the IEEE 4th Global Conference on Consumer Electronics, 2015
A score-based classification method for identifying hardware-trojans at gate-level netlists.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
A bit-write reduction method based on error-correcting codes for non-volatile memories.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
Improved monitoring-path selection algorithm for suspicious timing error prediction based timing speculation.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
Image synthesis circuit design using selector-logic-based alpha blending and its FPGA implementation.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
2014
IPSJ Trans. Syst. LSI Des. Methodol., 2014
Energy-efficient High-level Synthesis for HDR Architecture with Multi-stage Clock Gating.
IPSJ Trans. Syst. LSI Des. Methodol., 2014
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014
Throughput driven check point selection in suspicious timing error prediction based designs.
Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014
Linear and bi-linear interpolation circuits using selector logics and their evaluations.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
An area-overhead-oriented monitoring-path selection algorithm for suspicious timing error prediction.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014
A floorplan-driven high-level synthesis algorithm with operation chainings using chaining enumeration.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014
A write-reducing and error-correcting code generation method for non-volatile memories.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014
A floorplan-aware high-level synthesis algorithm for multiplexer reduction targeting FPGA designs.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014
2013
J. Inf. Process., 2013
Energy-efficient High-level Synthesis for HDR Architectures with Clock Gating Based on Concurrency-oriented Scheduling.
IPSJ Trans. Syst. LSI Des. Methodol., 2013
A High-Speed Trace-Driven Cache Configuration Simulator for Dual-Core Processor L1 Caches.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013
A Thermal-Aware High-Level Synthesis Algorithm for RDR Architectures through Binding and Allocation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013
Floorplan Driven Architecture and High-Level Synthesis Algorithm for Dynamic Multiple Supply Voltages.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013
An energy-efficient high-level synthesis algorithm incorporating interconnection delays and dynamic multiple supply voltages.
Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013
Proceedings of the IEEE 19th Pacific Rim International Symposium on Dependable Computing, 2013
Proceedings of the International Symposium on Quality Electronic Design, 2013
A partial redundant fault-secure high-level synthesis algorithm for RDR architectures.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Concurrent faulty clock detection for crypto circuits against clock glitch based DFA.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Energy evaluation for two-level on-chip cache with non-volatile memory on mobile processors.
Proceedings of the IEEE 10th International Conference on ASIC, 2013
Proceedings of the IEEE 10th International Conference on ASIC, 2013
2012
IEEE Trans. Very Large Scale Integr. Syst., 2012
A Fast Weighted Adder by Reducing Partial Product for Reconstruction in Super-Resolution.
IPSJ Trans. Syst. LSI Des. Methodol., 2012
IPSJ Trans. Syst. LSI Des. Methodol., 2012
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012
A Locality-Aware Hybrid NoC Configuration Algorithm Utilizing the Communication Volume among IP Cores.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012
MH<sup>4</sup> : multiple-supply-voltages aware high-level synthesis for high-integrated and high-frequency circuits for HDR architectures.
IEICE Electron. Express, 2012
Dynamically changeable secure scan architecture against scan-based side channel attack.
Proceedings of the International SoC Design Conference, 2012
Proceedings of the International SoC Design Conference, 2012
A novel BMNoC configuration algorithm utilizing communication volume and locality among cores.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
An energy-efficient high-level synthesis algorithm for huddle-based distributed-register architectures.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Weighted adders with selector logics for super-resolution and its FPGA-based evaluation.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012
State dependent scan flip-flop with key-based configuration against scan-based side channel attack on RSA circuit.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012
2011
A Fast Selector-Based Subtract-Multiplication Unit and Its Application to Butterfly Unit.
IPSJ Trans. Syst. LSI Des. Methodol., 2011
IPSJ Trans. Syst. LSI Des. Methodol., 2011
IPSJ Trans. Syst. LSI Des. Methodol., 2011
IPSJ Trans. Syst. LSI Des. Methodol., 2011
Greedy Algorithm for the On-Chip Decoupling Capacitance Optimization to Satisfy the Voltage Drop Constraint.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011
Greedy Optimization Algorithm for the Power/Ground Network Design to Satisfy the Voltage Drop Constraint.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011
IEICE Electron. Express, 2011
2010
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010
Performance-driven high-level synthesis with floorplan for GDR architectures and its evaluation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
State-dependent changeable scan architecture against scan-based side channel attacks.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
A fast selector-based subtract-multiplication unit and its application to Radix-2 butterfly unit.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010
BusMesh NoC: A novel NoC architecture comprised of bus-based connection and global mesh routers.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010
2009
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
Unified Dual-Radix Architecture for Scalable Montgomery Multiplications in <i>GF</i>(<i>P</i>) and <i>GF</i>(2<sup><i>n</i></sup>).
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
X-Handling for Current X-Tolerant Compactors with More Unknowns and Maximal Compaction.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
Floorplan-Aware High-Level Synthesis for Generalized Distributed-Register Architectures.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
Proceedings of the 2009 IEEE International Test Conference, 2009
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
2008
IPSJ Trans. Syst. LSI Des. Methodol., 2008
Low Power LDPC Code Decoder Architecture Based on Intermediate Message Compression Technique.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008
A Unified Test Compression Technique for Scan Stimulus and Unknown Masking Data with No Test Loss.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008
IEICE Trans. Inf. Syst., 2008
Scalable unified dual-radix architecture for Montgomery multiplication in GF(P) and GF(2<sup>n</sup>).
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
FIR filter design on Flexible Engine/Generic ALU array and its dedicated synthesis algorithm.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008
Dynamically reconfigurable architecture for multi-rate compatible regular LDPC decoding.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008
2007
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
2006
IEICE Trans. Electron., 2006
Power-Efficient LDPC Decoder Architecture Based on Accelerated Message-Passing Schedule.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006
Selective Low-Care Coding: A Means for Test Data Compression in Circuits with Multiple Scan Chains.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
FCSCAN: an efficient multiscan-based test compression technique for test cost reduction.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
An interface-circuit synthesis method with configurable processor core in IP-based SoC designs.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
2005
A SIMD Instruction Set and Functional Unit Synthesis Algorithm with SIMD Operation Decomposition.
IEICE Trans. Inf. Syst., 2005
IEICE Trans. Inf. Syst., 2005
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005
Sub-operation parallelism optimization in SIMD processor synthesis and its experimental evaluations.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
2004
Alternative Run-Length Coding through Scan Chain Reconfiguration for Joint Minimization of Test Data Volume and Power Consumption in Scan Test.
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
A cosynthesis algorithm for application specific processors with heterogeneous datapaths.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
2003
A Hardware/Software Cosynthesis System for Processor Cores with Content Addressable Memories.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003
A Hardware/Software Partitioning Algorithm for Processor Cores with Packed SIMD-Type Instructions.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003
A Retargetable Simulator Generator for DSP Processor Cores with Packed SIMD-type Instructions.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003
2002
A High-Level Energy-Optimizing Algorithm for System VLSIs Based on Area/Time/Power Estimation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002
An algorithm of hardware unit generation for processor core synthesis with packed SIMD type instructions.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002
2001
Proceedings of ASP-DAC 2001, 2001
2000
An area/time optimizing algorithm in high-level synthesis for control-based hardwares (short paper).
Proceedings of ASP-DAC 2000, 2000
1999
A Simultaneous Placement and Global Routing Algorithm for FPGAs with Power Optimization.
J. Circuits Syst. Comput., 1999
A Hardware/Software Partitioning Algorithm for Processor Cores of Digital Signal Processing.
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999
1998
Maple-opt: a performance-oriented simultaneous technology mapping, placement, and global routing algorithm for FPGAs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998
An Incremental Placement and Global Routing Algorithm for Field-Programmable Gate Arrays.
Proceedings of the ASP-DAC '98, 1998
A High-Level Synthesis System for Digital Signal Processing Based on Enumerating Data-Flow Graphs.
Proceedings of the ASP-DAC '98, 1998
1997
A Performance-Oriented Circuit Partitioning Algorithm with Logic-Block Replication for Multi-FPGA Systems.
J. Circuits Syst. Comput., 1997
A simultaneous placement and global routing algorithm with path length constraints for transport-processing FPGAs.
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997
1995
Maple-opt: a simultaneous technology mapping, placement, and global routing algorithm FPGAs with performance optimization.
Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995
1994
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994
A simultaneous technology mapping, placement, and global routing algorithm for field-programmable gate arrays.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994