Hiroyuki Sakai

Orcid: 0009-0006-6304-6358

Affiliations:
  • Tokyo Institute of Technology, Japan


According to our database1, Hiroyuki Sakai authored at least 18 papers between 2023 and 2025.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2025
A 640-Gb/s 4 × 4-MIMO D-Band CMOS Transceiver Chipset.
IEEE J. Solid State Circuits, April, 2025

A 2.5 dB noise figure 28 GHz current-reused noise-cancelling LNA with g<sub>m</sub>-boosting in 65 nm CMOS for millimeter-wave MIMO applications.
IEICE Electron. Express, 2025

A LEO Satellite Mounted 256-Element 19 GHz CMOS Phased-Array Transmitter With On-Chip Amplitude and Phase Monitor.
IEEE Access, 2025

5.6 A Power-Efficient CORDIC-Less Digital Polar Transmitter Using 1b DSM-Based PA Supporting 256-QAM.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025

11.1 A 256-Element Ka-Band CMOS Phased-Array Receiver Using Switch-Type Quadrature-Hybrid-First Architecture for Small Satellite Constellations.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025

A 4-Stream 8-Element Time-Division MIMO Phased-Array Receiver for 5G NR and Beyond Achieving 9.6Gbps Data Rate.
Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025

A D-Band CMOS Transceiver Chipset Supporting 640Gb/s Date Rate with 4?4 Line-of-Sight MIMO.
Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025

2024
A Sub-THz Full-Duplex Phased-Array Transceiver With Self-Interference Cancellation and LO Feedthrough Suppression.
IEEE J. Solid State Circuits, April, 2024

A 28GHz 4-Stream Time-Division MIMO Phased-Array Receiver Utilizing Nyquist-Rate Fast Beam Switching for 5G and Beyond.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

A 640-Gb/s 4×4-MIMO D-Band CMOS Transceiver Chipset.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

24.3 A 236-to-266GHz 4-Element Amplifier-Last Phased-Array Transmitter in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

A Compact D-Band Phase Shifter with 0.1-degree Phase Resolution and 0.8-degree RMS Phase Error in 65 nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2024

35-60GHz Switchless IF Bi-Directional Amplifier Using 65nm CMOS for 300GHz-Band Transceivers.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2024

2023
A Low-Power 256-Element Ka-Band CMOS Phased-Array Receiver With On-Chip Distributed Radiation Sensors for Small Satellite Constellations.
IEEE J. Solid State Circuits, December, 2023

A Sub-THz Full-Duplex Phased-Array Transceiver with Self-Interference Cancellation and LO Feedthrough Suppression.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

A Small-Satellite-Mounted 256-Element Ka-Band CMOS Phased-Array Transmitter Achieving 63.8dBm EIRP Under 26.6W Power Consumption Using Single/Dual Circular Polarization Active Coupler.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

A 2.95mW/element Ka-band CMOS Phased-Array Receiver Utilizing On-Chip Distributed Radiation Sensors in Low-Earth-Orbit Small Satellite Constellation.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

A Dual-Mode Bi-Directional CMOS Mixer Using Push-Push Doubler for 300GHz-Band Transceivers.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023


  Loading...