Hans Herdian

Orcid: 0000-0002-8667-3892

According to our database1, Hans Herdian authored at least 21 papers between 2016 and 2026.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
A 142-164-GHz Phased-Array AiP Module With High-Power-Density and High-Efficiency Transceiver in 65-nm CMOS for 6G UE.
IEEE J. Solid State Circuits, April, 2026

A 52 Gb/s 8.9-dBm EIRP 300-GHz-Band Amplifier-Last Outphasing Transmitter With Path Mismatch Calibration in 65-nm CMOS.
IEEE J. Solid State Circuits, April, 2026

2025
A 640-Gb/s 4 × 4-MIMO D-Band CMOS Transceiver Chipset.
IEEE J. Solid State Circuits, April, 2025

A 160-Gb/s D-Band Bi-Directional CMOS Mixer Covering 112-170 GHz for 6G Transceivers.
IEEE Solid State Circuits Lett., 2025

Experimental Testbed for Frequency-Division Multiplexed Joint Radar-Communication System Validation in D-Band Using a 65-nm CMOS Communication Transceiver.
IEEE Access, 2025

A D-Band CMOS Transceiver Chipset Supporting 640Gb/s Date Rate with 4?4 Line-of-Sight MIMO.
Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025

2024
A Sub-THz Full-Duplex Phased-Array Transceiver With Self-Interference Cancellation and LO Feedthrough Suppression.
IEEE J. Solid State Circuits, April, 2024

A 640-Gb/s 4×4-MIMO D-Band CMOS Transceiver Chipset.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

24.3 A 236-to-266GHz 4-Element Amplifier-Last Phased-Array Transmitter in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

35-60GHz Switchless IF Bi-Directional Amplifier Using 65nm CMOS for 300GHz-Band Transceivers.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2024

2023
A Ka-Band Deployable Active Phased Array Transmitter Fabricated on 4-Layer Liquid Crystal Polymer Substrate for Small-Satellite Mount.
IEEE Access, 2023

A Sub-THz Full-Duplex Phased-Array Transceiver with Self-Interference Cancellation and LO Feedthrough Suppression.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

A Small-Satellite-Mounted 256-Element Ka-Band CMOS Phased-Array Transmitter Achieving 63.8dBm EIRP Under 26.6W Power Consumption Using Single/Dual Circular Polarization Active Coupler.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

2021
A 32-kHz-Reference 2.4-GHz Fractional-N Oversampling PLL With 200-kHz Loop Bandwidth.
IEEE J. Solid State Circuits, 2021

32.7 A 32kHz-Reference 2.4GHz Fractional-N Oversampling PLL with 200kHz Loop Bandwidth.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

Dual-Layer Proton Irradiation for Creating Thermally-Stable High-Resistivity Region in Si CMOS Substrate.
Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021

2019
ULPAC: A Miniaturized Ultralow-Power Atomic Clock.
IEEE J. Solid State Circuits, 2019

A Power-Efficient Pulse-VCO for Chip-Scale Atomic Clock.
IEICE Trans. Electron., 2019

0.2mW 70Fsrms-Jitter Injection-Locked PLL Using De-Sensitized SSPD-Based Injecting-Time Self-Alignment Achieving -270dB FoM and -66dBc Reference Spur.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

Ultra-Low-Power Atomic Clock for Satellite Constellation with 2.2×10<sup>-12</sup> Long-Term Allan Deviation Using Cesium Coherent Population Trapping.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2016
FPGA implementation of template matching using binary sum of absolute difference.
Proceedings of the 6th International Conference on System Engineering and Technology, 2016


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