Hisanori Aikawa

According to our database, Hisanori Aikawa authored at least 3 papers between 2006 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2025

30.6 A 64Gb DDR4 STT-MRAM Using a Time-Controlled Discharge-Reading Scheme for a .001681µm 1T-1MTJ Cross-Point Cell.

Kosuke Hatsuda, Katsuhiko Hoya, Ryosuke Takizawa, Fumiyoshi Matsuoka, Takaya Yasuda, Akira Katayama, Tadashi Miyakawa, Kazuyo Senju, Kazuki Okawa, Yuka Furukawa, Yu Shimada, Katsuya Kotake, Sayaka Hirokawa, Min Chul Shin, Dong Keun Kim, Tae Ho Kim, Kyunghoon Kim, Hisanori Aikawa, Jeonghwan Song, Toshihiko Nagase, Soo Man Seo, Soo Gil Kim, Seonyong Cha

Proceedings of the IEEE International Solid-State Circuits Conference, 2025

2008

A Statistical Model for Assessing the Fault Tolerance of Variable Switching Currents for a 1Gb Spin Transfer Torque Magnetoresistive Random Access Memory.

Yoshiaki Asao, Masayoshi Iwayama, Kenji Tsuchida, Akihiro Nitayama, Hiroaki Yoda, Hisanori Aikawa, Sumio Ikegawa, Tatsuya Kishi

Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

2006

MRAM Write Error Categorization with QCKB.

Yuui Shimizu, Hisanori Aikawa, Keiji Hosotani, Naoharu Shimomura, Tadashi Kai, Yoshihiro Ueda, Yoshiaki Asao, Yoshihisa Iwata, Kenji Tsuchida, Sumio Ikegawa

Proceedings of the 14th IEEE International Workshop on Memory Technology, 2006