Kosuke Hatsuda

According to our database, Kosuke Hatsuda authored at least 7 papers between 2005 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2019

A perspective on NVRAM technology for future computing system.

Katsuhiko Hoya, Kosuke Hatsuda, Kenji Tsuchida, Yohji Watanabe, Yusuke Shirota, Tatsunori Kanai

Proceedings of the International Symposium on VLSI Design, Automation and Test, 2019

2011

A 128 Mb Chain FeRAM and System Design for HDD Application and Enhanced HDD Performance.

Daisaburo Takashima, Yasushi Nagadomi, Kosuke Hatsuda, Yohji Watanabe, Shuso Fujii

IEEE J. Solid State Circuits, 2011

Generation of Accurate Reference Current for Data Sensing in High-Density Memories by Averaging Multiple Pairs of Dummy Cells.

Takashi Ohsawa, Kosuke Hatsuda, Katsuyuki Fujita, Fumiyoshi Matsuoka, Tomoki Higashi

IEEE J. Solid State Circuits, 2011

2010

A 1.6 GB/s DDR2 128 Mb Chain FeRAM With Scalable Octal Bitline and Sensing Schemes.

Hidehiro Shiga, Daisaburo Takashima, Shinichiro Shiratake, Katsuhiko Hoya, Tadashi Miyakawa, Ryu Ogiwara, Ryo Fukuda, Ryosuke Takizawa, Kosuke Hatsuda, Fumiyoshi Matsuoka, Yasushi Nagadomi, Daisuke Hashimoto, Hisaaki Nishimura, Takeshi Hioka, Sumiko M. Doumae, Shoichi Shimizu, Mitsumo Kawano, Toyoki Taguchi, Yohji Watanabe, Shuso Fujii, Tohru Ozaki, Hiroyuki Kanaya, Yoshinori Kumura, Yoshiro Shimojo, Yuki Yamada, Yoshihiro Minami, Susumu Shuto, Koji Yamakawa, Soichi Yamazaki, Iwao Kunishima, Takeshi Hamamoto, Akihiro Nitayama, Tohru Furuyama

IEEE J. Solid State Circuits, 2010

2009

A 1.6GB/s DDR2 128Mb chain FeRAM with scalable octal bitline and sensing schemes.

Hidehiro Shiga, Daisaburo Takashima, Shinichiro Shiratake, Katsuhiko Hoya, Tadashi Miyakawa, Ryu Ogiwara, Ryo Fukuda, Ryosuke Takizawa, Kosuke Hatsuda, Fumiyoshi Matsuoka, Yasushi Nagadomi, Daisuke Hashimoto, Hisaaki Nishimura, Takeshi Hioka, Sumiko M. Doumae, Shoichi Shimizu, Mitsumo Kawano, Toyoki Taguchi, Yohji Watanabe, Shuso Fujii, Tohru Ozaki, Hiroyuki Kanaya, Yoshinori Kumura, Yoshiro Shimojo, Yuki Yamada, Yoshihiro Minami, Susumu Shuto, Koji Yamakawa, Soichi Yamazaki, Iwao Kunishima, Takeshi Hamamoto, Akihiro Nitayama, Tohru Furuyama

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2006

Design of a 128-mb SOI DRAM using the floating body cell (FBC).

Takashi Ohsawa, Katsuyuki Fujita, Kosuke Hatsuda, Tomoki Higashi, Tomoaki Shino, Yoshihiro Minami, Hiroomi Nakajima, Mutsuo Morikado, Kazumi Inoh, Takeshi Hamamoto, Shigeyoshi Watanabe, Shuso Fujii, Tohru Furuyama

IEEE J. Solid State Circuits, 2006

2005

A 333MHz random cycle DRAM using the floating body cell.

Kosuke Hatsuda, Katsuyuki Fujita, Takashi Ohsawa

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005