Hong-Ting Lin

According to our database, Hong-Ting Lin authored at least 5 papers between 2011 and 2014.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2014

Pulsed-Latch Utilization for Clock-Tree Power Optimization.

Hong-Ting Lin, Yi-Lin Chuang, Zong-Han Yang, Tsung-Yi Ho

IEEE Trans. Very Large Scale Integr. Syst., 2014

2012

Load-balanced clock tree synthesis with adjustable delay buffer insertion for clock skew reduction in multiple dynamic supply voltage designs.

Kuan-Yu Lin, Hong-Ting Lin, Tsung-Yi Ho, Chia-Chun Tsai

ACM Trans. Design Autom. Electr. Syst., 2012

2011

Pulsed-latch-based clock tree migration for dynamic power reduction.

Hong-Ting Lin, Yi-Lin Chuang, Tsung-Yi Ho

Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

PRICE: Power reduction by placement and clock-network co-synthesis for pulsed-latch designs.

Yi-Lin Chuang, Hong-Ting Lin, Tsung-Yi Ho, Yao-Wen Chang, Diana Marculescu

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

An efficient algorithm of adjustable delay buffer insertion for clock skew minimization in multiple dynamic supply voltage designs.

Kuan-Yu Lin, Hong-Ting Lin, Tsung-Yi Ho

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011