Yao-Wen Chang

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Intelligent Design Automation for 2.5/3D Heterogeneous SoC Integration.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Time-Division Multiplexing Based System-Level FPGA Routing for Logic Verification.

[BibT_eX]

[DOI]

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

A Provably Good Wavelength-Division-Multiplexing-Aware Clustering Algorithm for On-Chip Optical Routing.

[BibT_eX]

[DOI]

Yu-Sheng Lu

Sheng-Jung Yu

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

Topological Structure and Physical Layout Codesign for Wavelength-Routed Optical Networks-on-Chip.

[BibT_eX]

[DOI]

Yu-Sheng Lu

Sheng-Jung Yu

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

Latch Clustering for Timing-Power Co-Optimization.

[BibT_eX]

[DOI]

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

Hamiltonian Path Based Mixed-Cell-Height Legalization for Neighbor Diffusion Effect Mitigation.

[BibT_eX]

[DOI]

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

An Efficient EPIST Algorithm for Global Placement with Non-Integer Multiple-Height Cells *.

[BibT_eX]

[DOI]

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

Unified Redistribution Layer Routing for 2.5D IC Packages.

[BibT_eX]

[DOI]

Chun-Han Chiang

Fu-Yu Chuang

Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019

Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory.

[BibT_eX]

[DOI]

Ibrahim Abe M. Elfadel

Mehran Mozaffari Kermani

IEEE Trans. Very Large Scale Integr. Syst., 2019

DSA-Compliant Routing for 2-D Patterns Using Block Copolymer Lithography.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Multiview Contouring for Breast Tumor on Magnetic Resonance Imaging.

[BibT_eX]

[DOI]

J. Digit. Imaging, 2019

Analytical Mixed-Cell-Height Legalization Considering Average and Maximum Movement Minimization.

[BibT_eX]

[DOI]

Proceedings of the 2019 International Symposium on Physical Design, 2019

Graph- and ILP-Based Cut Redistribution for Two-Dimensional Directed Self-Assembly.

[BibT_eX]

[DOI]

Zhan-Ling Wang

Proceedings of the International Conference on Computer-Aided Design, 2019

Timing-Aware Fill Insertions with Design-Rule and Density Constraints.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2019

Analytical Placement with 3D Poisson's Equation and ADMM Based Optimization for Large-Scale 2.5D Heterogeneous FPGAs.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2019

Obstacle-Aware Group-Based Length-Matching Routing for Pre-Assignment Area-I/O Flip-Chip Designs.

[BibT_eX]

[DOI]

Yu-Hsuan Chang

Hsiang-Ting Wen

Proceedings of the International Conference on Computer-Aided Design, 2019

BiG: A Bivariate Gradient-Based Wirelength Model for Analytical Circuit Placement.

[BibT_eX]

[DOI]

Fan-Keng Sun

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

MDP-trees: multi-domain macro placement for ultra large-scale mixed-size designs.

[BibT_eX]

[DOI]

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018

Provably Good Max-Min-m-Neighbor-TSP-Based Subfield Scheduling for Electron-Beam Photomask Fabrication.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2018

NTUplace4dr: A Detailed-Routing-Driven Placer for Mixed-Size Circuit Designs With Technology and Region Constraints.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Mixed-cell-height legalization considering technology and region constraints.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2018

Analytical solution of Poisson's equation and its application to VLSI global placement.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2018

Mixed-cell-height placement considering drain-to-drain abutment.

[BibT_eX]

[DOI]

Yu-Wei Tseng

Proceedings of the International Conference on Computer-Aided Design, 2018

A multithreaded initial detailed routing algorithm considering global routing guides.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2018

Mixed-cell-height placement with complex minimum-implant-area constraints.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2018

Novel proximal group ADMM for placement considering fogging and proximity effects.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2018

Simultaneous partitioning and signals grouping for time-division multiplexing in 2.5D FPGA-based systems.

[BibT_eX]

[DOI]

Shih-Chun Chen

Richard Sun

Proceedings of the International Conference on Computer-Aided Design, 2018

Generalized augmented lagrangian and its applications to VLSI global placement.

[BibT_eX]

[DOI]

Proceedings of the 55th Annual Design Automation Conference, 2018

DSA-friendly detailed routing considering double patterning and DSA template assignments.

[BibT_eX]

[DOI]

Hai-Juan Yu

Proceedings of the 55th Annual Design Automation Conference, 2018

Efficient multi-layer obstacle-avoiding region-to-region rectilinear steiner tree construction.

[BibT_eX]

[DOI]

Jie-Hong Roland Jiang

Proceedings of the 55th Annual Design Automation Conference, 2018

WB-trees: a meshed tree representation for FinFET analog layout designs.

[BibT_eX]

[DOI]

Yu-Sheng Lu

Yu-Hsuan Chang

Proceedings of the 55th Annual Design Automation Conference, 2018

2017

Editorial.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

Nanowire-Aware Routing Considering High Cut Mask Complexity.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Cut Redistribution With Directed-Self-Assembly Templates for Advanced 1-D Gridded Layouts.

[BibT_eX]

[DOI]

Zhi-Wen Lin

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

An Interview With Professor Chenming Hu, Father of 3D Transistors.

[BibT_eX]

[DOI]

IEEE Des. Test, 2017

Generalized Force Directed Relaxation with Optimal Regions and Its Applications to Circuit Placement.

[BibT_eX]

[DOI]

Proceedings of the 2017 ACM on International Symposium on Physical Design, 2017

Blockage-aware terminal propagation for placement wirelength minimization.

[BibT_eX]

[DOI]

Sheng-Wei Yang

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Mixed-cell-height detailed placement considering complex minimum-implant-area constraints.

[BibT_eX]

[DOI]

Yen-Yi Wu

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Redistribution layer routing for wafer-level integrated fan-out package-on-packages.

[BibT_eX]

[DOI]

Ting-Chou Lin

Chia-Chih Chi

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Clock-aware placement for large-scale heterogeneous FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

An integrated-spreading-based macro-refining algorithm for large-scale mixed-size circuit designs.

[BibT_eX]

[DOI]

Szu-To Chen

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

FPGA placement and routing.

[BibT_eX]

[DOI]

Shih-Chun Chen

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

A novel damped-wave framework for macro placement.

[BibT_eX]

[DOI]

Chin-Hao Chang

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Detailed Placement for Two-Dimensional Directed Self-Assembly Technology.

[BibT_eX]

[DOI]

Zhi-Wen Lin

Proceedings of the 54th Annual Design Automation Conference, 2017

Graph-Based Logic Bit Slicing for Datapath-Aware Placement.

[BibT_eX]

[DOI]

Proceedings of the 54th Annual Design Automation Conference, 2017

Fogging Effect Aware Placement in Electron Beam Lithography.

[BibT_eX]

[DOI]

Yu-Chen Huang

Proceedings of the 54th Annual Design Automation Conference, 2017

Toward Optimal Legalization for Mixed-Cell-Height Circuit Designs.

[BibT_eX]

[DOI]

Proceedings of the 54th Annual Design Automation Conference, 2017

An effective legalization algorithm for mixed-cell-height standard cells.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016

Fast Lithographic Mask Optimization Considering Process Variation.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Layout-Dependent Effects-Aware Analytical Analog Placement.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Overlay-Aware Detailed Routing for Self-Aligned Double Patterning Lithography Using the Cut Process.

[BibT_eX]

[DOI]

Iou-Jen Liu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Simultaneous EUV Flare Variation Minimization and CMP Control by Coupling-Aware Dummification.

[BibT_eX]

[DOI]

Hui-Ju Katherine Chiang

Chi-Yuan Liu

Jie-Hong R. Jiang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Double-Patterning Aware DSA Template Guided Cut Redistribution for Advanced 1-D Gridded Designs.

[BibT_eX]

[DOI]

Zhi-Wen Lin

Proceedings of the 2016 on International Symposium on Physical Design, 2016

DSA-compliant routing for two-dimensional patterns using block copolymer lithography.

[BibT_eX]

[DOI]

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

VCR: simultaneous via-template and cut-template-aware routing for directed self-assembly technology.

[BibT_eX]

[DOI]

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Redistribution layer routing for integrated fan-out wafer-level chip-scale packages.

[BibT_eX]

[DOI]

Bo-Qiao Lin

Ting-Chou Lin

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

QB-trees: towards an optimal topological representation and its applications to analog layout designs.

[BibT_eX]

[DOI]

I-Peng Wu

Proceedings of the 53rd Annual Design Automation Conference, 2016

Minimum-implant-area-aware detailed placement with spacing constraints.

[BibT_eX]

[DOI]

Kai-Han Tseng

Charles C. C. Liu

Proceedings of the 53rd Annual Design Automation Conference, 2016

Timing-driven cell placement optimization for early slack histogram compression.

[BibT_eX]

[DOI]

Proceedings of the 53rd Annual Design Automation Conference, 2016

Recent research development and new challenges in analog layout synthesis.

[BibT_eX]

[DOI]

Mark Po-Hung Lin

Chih-Ming Hung

Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

Circular-contour-based obstacle-aware macro placement.

[BibT_eX]

[DOI]

Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015

Stitch-Aware Routing for Multiple E-Beam Lithography.

[BibT_eX]

[DOI]

Iou-Jen Liu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Coupling-Aware Length-Ratio-Matching Routing for Capacitor Arrays in Analog Integrated Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Provably Good Max-Min-m-neighbor-TSP-Based Subfield Scheduling for Electron-Beam Photomask Fabrication.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Detailed-Routability-Driven Analytical Placement for Mixed-Size Designs with Technology and Region Constraints.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Cutting structure-aware analog placement based on self-aligned double patterning with e-beam lithography.

[BibT_eX]

[DOI]

Kai-Han Tseng

Proceedings of the 52nd Annual Design Automation Conference, 2015

Routing-architecture-aware analytical placement for heterogeneous FPGAs.

[BibT_eX]

[DOI]

Sheng-Yen Chen

Proceedings of the 52nd Annual Design Automation Conference, 2015

EUV and e-beam manufacturability: challenges and solutions.

[BibT_eX]

[DOI]

Ru-Gun Liu

Proceedings of the 52nd Annual Design Automation Conference, 2015

Detailed-Routing-Driven analytical standard-cell placement.

[BibT_eX]

[DOI]

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

Non-stitch triple patterning-aware routing based on conflict graph pre-coloring.

[BibT_eX]

[DOI]

Po-Ya Hsu

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

Layout decomposition for Spacer-is-Metal (SIM) self-aligned double patterning.

[BibT_eX]

[DOI]

Yi-Shu Tai

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014

Nonuniform Multilevel Analog Routing With Matching Constraints.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

NTUplace4h: A Novel Routability-Driven Placement Algorithm for Hierarchical Mixed-Size Circuit Designs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Obstacle-Avoiding Free-Assignment Routing for Flip-Chip Designs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

A Novel Layout Decomposition Algorithm for Triple Patterning Lithography.

[BibT_eX]

[DOI]

Wei-Yu Chen

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Buffered clock tree synthesis considering self-heating effects.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Low Power Electronics and Design, 2014

Design and Implementation of a RESTful Notification Service.

[BibT_eX]

[DOI]

Proceedings of the Intelligent Systems and Applications, 2014

Simultaneous EUV flare- and CMP-aware placement.

[BibT_eX]

[DOI]

Chi-Yuan Liu

Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

Efficient and effective packing and analytical placement for large-scale heterogeneous FPGAs.

[BibT_eX]

[DOI]

Yu-Chen Chen

Sheng-Yen Chen

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Simultaneous EUV Flare Variation Minimization and CMP Control with Coupling-Aware Dummification.

[BibT_eX]

[DOI]

Chi-Yuan Liu

Hui-Ju Katherine Chiang

Jie-Hong R. Jiang

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

A New Asynchronous Pipeline Template for Power and Performance Optimization.

[BibT_eX]

[DOI]

Kuan-Hsien Ho

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Routability-Driven Blockage-Aware Macro Placement.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Functional ECO Using Metal-Configurable Gate-Array Spare Cells.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013

TSV-Aware Analytical Placement for 3-D IC Designs Based on a Novel Weighted-Average Wirelength Model.

[BibT_eX]

[DOI]

Valeriy Balabanov

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Escape Routing for Staggered-Pin-Array PCBs.

[BibT_eX]

[DOI]

Yuan-Kai Ho

Hsu-Chieh Lee

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Graph-Based Subfield Scheduling for Electron-Beam Photomask Fabrication.

[BibT_eX]

[DOI]

Wei-Yu Chen

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

ECO Optimization Using Metal-Configurable Gate-Array Spare Cells.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Circuit placement challenges: technical perspective.

[BibT_eX]

[DOI]

Commun. ACM, 2013

Simultaneous OPC- and CMP-aware routing based on accurate closed-form modeling.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Physical Design, 2013

Simultaneous analog placement and routing with current flow and current density considerations.

[BibT_eX]

[DOI]

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

An efficient and effective analytical placer for FPGAs.

[BibT_eX]

[DOI]

Tzu-Hen Lin

Pritha Banerjee

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Routability-driven placement for hierarchical mixed-size circuit designs.

[BibT_eX]

[DOI]

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Multiple chip planning for chip-interposer codesign.

[BibT_eX]

[DOI]

Yuan-Kai Ho

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Double patterning lithography-aware analog placement.

[BibT_eX]

[DOI]

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Symmetrical buffered clock-tree synthesis with supply-voltage alignment.

[BibT_eX]

[DOI]

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

Layer minimization in escape routing for staggered-pin-array PCBs.

[BibT_eX]

[DOI]

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012

Fast Timing-Model Independent Buffered Clock-Tree Synthesis.

[BibT_eX]

[DOI]

Xin-Wei Shih

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

An Efficient Pre-Assignment Routing Algorithm for Flip-Chip Designs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Unified Analytical Global Placement for Large-Scale Mixed-Size Circuit Designs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

TRECO: Dynamic Technology Remapping for Timing Engineering Change Orders.

[BibT_eX]

[DOI]

Kuan-Hsien Ho

Jie-Hong Roland Jiang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Native-Conflict and Stitch-Aware Wire Perturbation for Double Patterning Technology.

[BibT_eX]

[DOI]

Szu-Yu Chen

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Timing ECO Optimization Via Bézier Curve Smoothing and Fixability Identification.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Statistical thermal modeling and optimization considering leakage power variations.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Non-uniform multilevel analog routing with matching constraints.

[BibT_eX]

[DOI]

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Obstacle-avoiding free-assignment routing for flip-chip designs.

[BibT_eX]

[DOI]

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

A chip-package-board co-design methodology.

[BibT_eX]

[DOI]

Hsu-Chieh Lee

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Simultaneous flare level and flare variation minimization with dummification in EUVL.

[BibT_eX]

[DOI]

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Structure-aware placement for datapath-intensive circuit designs.

[BibT_eX]

[DOI]

Sheng Chou

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Timing ECO optimization using metal-configurable gate-array spare cells.

[BibT_eX]

[DOI]

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011

Guest Editorial.

[BibT_eX]

[DOI]

Prashant Saxena

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Thermal-Driven Analog Placement Considering Device Matching.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Cross-Contamination Aware Design Methodology for Pin-Constrained Digital Microfluidic Biochips.

[BibT_eX]

[DOI]

Cliff Chiung-Yu Lin

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Simultaneous Layout Migration and Decomposition for Double Patterning Technology.

[BibT_eX]

[DOI]

Sani R. Nassif

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Voltage-Drop Aware Analytical Placement by Global Power Spreading for Mixed-Size Circuit Designs.

[BibT_eX]

[DOI]

Yi-Lin Chuang

Po-Wei Lee

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Pulsed-Latch Aware Placement for Timing-Integrity Optimization.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

A SAT-based routing algorithm for cross-referencing biochips.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Workshop on System Level Interconnect Prediction, 2011

A corner stitching compliant B∗-tree representation and its applications to analog placement.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Routability-driven analytical placement for mixed-size circuit designs.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

PRICE: Power reduction by placement and clock-network co-synthesis for pulsed-latch designs.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Heterogeneous B∗-trees for analog placement with symmetry and regularity considerations.

[BibT_eX]

[DOI]

Pang-Yen Chou

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

TSV-aware analytical placement for 3D IC designs.

[BibT_eX]

[DOI]

Valeriy Balabanov

Proceedings of the 48th Design Automation Conference, 2011

Simultaneous functional and timing ECO.

[BibT_eX]

[DOI]

Proceedings of the 48th Design Automation Conference, 2011

2010

ILP-Based Pin-Count Aware Design Methodology for Microfluidic Biochips.

[BibT_eX]

[DOI]

Cliff Chiung-Yu Lin

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Multilayer Global Routing With Via and Wire Capacity Considerations.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

ECO Timing Optimization Using Spare Cells and Technology Remapping.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Area-I/O Flip-Chip Routing for Chip-Package Co-Design Considering Signal Skews.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Predictive Formulae for OPC With Applications to Lithography-Friendly Routing.

[BibT_eX]

[DOI]

Guang-Wan Liao

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Design of an Omnidirectional Multibeam Transmitter for High-Speed Indoor Wireless Communications.

[BibT_eX]

[DOI]

Jaw-Luen Tang

EURASIP J. Wirel. Commun. Netw., 2010

Density gradient minimization with coupling-constrained dummy fill for CMP control.

[BibT_eX]

[DOI]

Szu-Jui Chou

Proceedings of the 2010 International Symposium on Physical Design, 2010

Efficient provably good OPC modeling and its applications to interconnect optimization.

[BibT_eX]

[DOI]

Shih-Lun Huang

Chung-Wei Lin

Proceedings of the 28th International Conference on Computer Design, 2010

High variation-tolerant obstacle-avoiding clock mesh synthesis with symmetrical driving trees.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Recent research development in flip-chip routing.

[BibT_eX]

[DOI]

Hsu-Chieh Lee

Po-Wei Lee

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Template-mask design methodology for double patterning technology.

[BibT_eX]

[DOI]

Sani R. Nassif

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Redundant-wires-aware ECO timing and mask cost optimization.

[BibT_eX]

[DOI]

Tzuo-Fan Chien

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Design-hierarchy aware mixed-size placement for routability optimization.

[BibT_eX]

[DOI]

Natarajan Viswanathan

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Native-conflict-aware wire perturbation for double patterning technology.

[BibT_eX]

[DOI]

Szu-Yu Chen

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Blockage-avoiding buffered clock-tree synthesis for clock latency-range and skew minimization.

[BibT_eX]

[DOI]

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

Three-dimensional integrated circuits (3D IC) floorplan and power/ground network co-synthesis.

[BibT_eX]

[DOI]

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009

T-trees: A tree-based representation for temporal and three-dimensional floorplanning.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2009

A Progressive-ILP-Based Routing Algorithm for the Synthesis of Cross-Referencing Biochips.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Analog Placement Based on Symmetry-Island Formulation.

[BibT_eX]

[DOI]

Mark Po-Hung Lin

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Voltage-Island Partitioning and Floorplanning Under Timing Constraints.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

An Integer-Linear-Programming-Based Routing Algorithm for Flip-Chip Designs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

A Novel Wire-Density-Driven Full-Chip Routing System for CMP Variation Control.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Essential Issues in Analytical Placement Algorithms.

[BibT_eX]

[DOI]

IPSJ Trans. Syst. LSI Des. Methodol., 2009

Post-floorplanning power/ground ring synthesis for multiple-supply-voltage designs.

[BibT_eX]

[DOI]

Diana Marculescu

Proceedings of the 2009 International Symposium on Physical Design, 2009

BIST design optimization for large-scale embedded memory cores.

[BibT_eX]

[DOI]

Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Spare-cell-aware multilevel analytical placement.

[BibT_eX]

[DOI]

Proceedings of the 46th Design Automation Conference, 2009

Flip-chip routing with unified area-I/O pad assignments for package-board co-design.

[BibT_eX]

[DOI]

Martin D. F. Wong

Proceedings of the 46th Design Automation Conference, 2009

High-performance global routing with fast overflow reduction.

[BibT_eX]

[DOI]

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008

Global Interconnect Planning.

[BibT_eX]

[DOI]

Cheng-Kok Koh

Evangeline F. Y. Young

Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

Packing Floorplan Representations.

[BibT_eX]

[DOI]

Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

BioRoute: A Network-Flow-Based Routing Algorithm for the Synthesis of Digital Microfluidic Biochips.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

An Efficient Graph-Based Algorithm for ESD Current Path Analysis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Multilayer Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Spanning Graphs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Spanning Graphs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

An Optimal Network-Flow-Based Simultaneous Diode and Jumper Insertion Algorithm for Antenna Fixing.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

MP-Trees: A Packing-Based Macro Placement Algorithm for Modern Mixed-Size Designs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs With Preplaced Blocks and Density Constraints.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Metal-Density-Driven Placement for CMP Variation and Routability.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

A New Multilevel Framework for Large-Scale Interconnect-Driven Floorplanning.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Full-Chip Routing Considering Double-Via Insertion.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Effective Wire Models for X-Architecture Placement.

[BibT_eX]

[DOI]

Yi-Lin Chuang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Multi-layer global routing considering via and wire capacities.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Routing for chip-package-board co-design considering differential pairs.

[BibT_eX]

[DOI]

Kuan-Hsien Ho

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Area-I/O flip-chip routing for chip-package co-design.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Constraint graph-based macro placement for modern mixed-size circuit designs.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

A progressive-ILP based routing algorithm for cross-referencing biochips.

[BibT_eX]

[DOI]

Proceedings of the 45th Design Automation Conference, 2008

Routability-driven analytical placement by net overlapping removal for large-scale mixed-size designs.

[BibT_eX]

[DOI]

Proceedings of the 45th Design Automation Conference, 2008

2007

Temporal floorplanning using the three-dimensional transitive closure subGraph.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2007

An Exact Jumper-Insertion Algorithm for Antenna Violation Avoidance/Fixing Considering Routing Obstacles.

[BibT_eX]

[DOI]

Jiang Hu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

An Optimal Jumper-Insertion Algorithm for Antenna Avoidance/Fixing.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Power/Ground Network and Floorplan Cosynthesis for Fast Design Convergence.

[BibT_eX]

[DOI]

Chen-Wei Liu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Multilevel Full-Chip Routing With Testability and Yield Enhancement.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

MBast-Tree: A Multilevel Floorplanner for Large-Scale Building-Module Design.

[BibT_eX]

[DOI]

Hsun-Cheng Lee

Hannah Honghua Yang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

A Network-Flow-Based RDL Routing Algorithmz for Flip-Chip Design.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Multilevel Full-Chip Gridless Routing With Applications to Optical-Proximity Correction.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Placement of defect-tolerant digital microfluidic biochips using the T-tree formulation.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2007

X-Route: An X-architecture full-chip multilevel router.

[BibT_eX]

[DOI]

Chen-Feng Chang

Proceedings of the 2007 IEEE International SOC Conference, 2007

Statistical circuit optimization considering device andinterconnect process variations.

[BibT_eX]

[DOI]

I-Jye Lin

Tsui-Yee Ling

Proceedings of the Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), 2007

A Statistical Approach to the Timing-Yield Optimization of Pipeline Circuits.

[BibT_eX]

[DOI]

Szu-Jui Chou

Jie-Hong Roland Jiang

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

Efficient obstacle-avoiding rectilinear steiner tree construction.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Symposium on Physical Design, 2007

X-architecture placement based on effective wire models.

[BibT_eX]

[DOI]

Yi-Lin Chuang

Proceedings of the 2007 International Symposium on Physical Design, 2007

Post-placement leakage optimization for partially dynamically reconfigurable FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

3D Video Applications and Intelligent Video Surveillance Camera and its VLSI Design.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE International Conference on Multimedia and Expo, 2007

BioRoute: a network-flow based routing algorithm for digital microfluidic biochips.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Efficient multi-layer obstacle-avoiding rectilinear Steiner tree construction.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

An efficient algorithm for statistical circuit optimization using Lagrangian relaxation.

[BibT_eX]

[DOI]

I-Jye Lin

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

An ILP algorithm for post-floorplanning voltage-island generation considering power-network planning.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

ECO timing optimization using spare cells.

[BibT_eX]

[DOI]

Yen-Pin Chen

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Novel wire density driven full-chip routing for CMP variation control.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

A Provably Good Approximation Algorithm for Power Optimization Using Multiple Supply Voltages.

[BibT_eX]

[DOI]

Proceedings of the 44th Design Automation Conference, 2007

An Integer Linear Programming Based Routing Algorithm for Flip-Chip Design.

[BibT_eX]

[DOI]

Proceedings of the 44th Design Automation Conference, 2007

MP-trees: A Packing-Based Macro Placement Algorithm for Mixed-Size Designs.

[BibT_eX]

[DOI]

Proceedings of the 44th Design Automation Conference, 2007

Recent Research and Emerging Challenges in Physical Design for Manufacturability/Reliability.

[BibT_eX]

[DOI]

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs.

[BibT_eX]

[DOI]

Proceedings of the Modern Circuit Placement, Best Practices and Results, 2007

Full-Chip Nanometer Routing Techniques.

[BibT_eX]

[DOI]

Tsung-Yi Ho

Sao-Jie Chen

Analog Circuits and Signal Processing, Springer, ISBN: 978-1-4020-6194-3, 2007

2006

Reliable crosstalk-driven interconnect optimization.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2006

RLC Coupling-Aware Simulation and On-Chip Bus Encoding for Delay Reduction.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

IEEE Standard 1500 Compatible Interconnect Diagnosis for Delay and Crosstalk Faults.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Modern Floorplanning Based on B*-Tree and Fast Simulated Annealing.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Multilevel routing with jumper insertion for antenna avoidance.

[BibT_eX]

[DOI]

Tsung-Yi Ho

Sao-Jie Chen

Integr., 2006

An optimal jumper insertion algorithm for antenna avoidance/fixing on general routing trees with obstacles.

[BibT_eX]

[DOI]

Jiang Hu

Proceedings of the 2006 International Symposium on Physical Design, 2006

Floorplan and power/ground network co-synthesis for fast design convergence.

[BibT_eX]

[DOI]

Chen-Wei Liu

Proceedings of the 2006 International Symposium on Physical Design, 2006

NTUplace2: a hybrid placer using partitioning and analytical techniques.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Symposium on Physical Design, 2006

Inductance extraction for general interconnect structures.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Current path analysis for electrostatic discharge protection.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Voltage island aware floorplanning for power and timing optimization.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

An optimal simultaneous diode/jumper insertion algorithm for antenna fixing.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

A high-quality mixed-size analytical placer considering preplaced blocks and density constraints.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Placement of digital microfluidic biochips using the t-tree formulation.

[BibT_eX]

[DOI]

Proceedings of the 43rd Design Automation Conference, 2006

Novel full-chip gridless routing considering double-via insertion.

[BibT_eX]

[DOI]

Proceedings of the 43rd Design Automation Conference, 2006

Simultaneous block and I/O buffer floorplanning for flip-chip design.

[BibT_eX]

[DOI]

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

A novel framework for multilevel full-chip gridless routing.

[BibT_eX]

[DOI]

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005

TCG: A transitive closure graph-based representation for general floorplans.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2005

Crosstalk- and performance-driven multilevel full-chip routing.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Reconfigurable Platform for Content Science Research.

[BibT_eX]

[DOI]

Proceedings of the 11th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2005), 2005

NTUplace: a ratio partitioning based placement algorithm for large-scale mixed-size designs.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Symposium on Physical Design, 2005

Modern floorplanning based on fast simulated annealing.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Symposium on Physical Design, 2005

Joint exploration of architectural and physical design spaces with thermal consideration.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

RLC coupling-aware simulation for on-chip buses and their encoding for delay reduction.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A routing algorithm for flip-chip design.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

IMF: interconnect-driven multilevel floorplanning for large-scale building-module designs.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

An exact jumper insertion algorithm for antenna effect avoidance/fixing.

[BibT_eX]

[DOI]

Proceedings of the 42nd Design Automation Conference, 2005

Multilevel full-chip routing for the X-based architecture.

[BibT_eX]

[DOI]

Proceedings of the 42nd Design Automation Conference, 2005

SoC test scheduling using the B-tree based floorplanning technique.

[BibT_eX]

[DOI]

Jen-Yi Wuu

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Placement with symmetry constraints for analog layout design using TCG-S.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Multilevel full-chip gridless routing considering optical proximity correction.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

Timing modeling and optimization under the transmission line model.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2004

TCG-S: orthogonal coupling of P*-admissible representations for general floorplans.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Simultaneous floor plan and buffer-block optimization.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

MR: a new framework for multilevel full-chip routing.

[BibT_eX]

[DOI]

Shih-Ping Lin

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

A clustering- and probability-based approach for time-multiplexed FPGA partitioning.

[BibT_eX]

[DOI]

Mango Chia-Tso Chao

Integr., 2004

Multilevel routing with antenna avoidance.

[BibT_eX]

[DOI]

Tsung-Yi Ho

Sao-Jie Chen

Proceedings of the 2004 International Symposium on Physical Design, 2004

RLC effects on worst-case switching pattern for on-chip buses.

[BibT_eX]

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Placement with Alignment and Performance Constraints Using the B*-Tree Representation.

[BibT_eX]

[DOI]

Meng-Chen Wu

Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

Temporal floorplanning using the T-tree formulation.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Efficient power/ground network analysis for power integrity-driven design methodology.

[BibT_eX]

[DOI]

Su-Wei Wu

Proceedings of the 41th Design Automation Conference, 2004

Temporal floorplanning using 3D-subTCG.

[BibT_eX]

[DOI]

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

Layout techniques for on-chip interconnect inductance reduction.

[BibT_eX]

[DOI]

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

Integrating buffer planning with floorplanning for simultaneous multi-objective optimization.

[BibT_eX]

[DOI]

Yi-Hui Cheng

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003

Corner sequence - a P-admissible floorplan representation with a worst case linear-time packing scheme.

[BibT_eX]

[DOI]

Shih-Ping Lin

IEEE Trans. Very Large Scale Integr. Syst., 2003

Rectilinear block placement using B*-trees.

[BibT_eX]

[DOI]

Yun-Chih Chang

ACM Trans. Design Autom. Electr. Syst., 2003

Analysis of FPGA/FPIC switch modules.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2003

A Fast Crosstalk- and Performance-Driven Multilevel Routing System.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Multilevel floorplanning/placement for large-scale modules using B*-trees.

[BibT_eX]

[DOI]

Proceedings of the 40th Design Automation Conference, 2003

Graph matching-based algorithms for array-based FPGA segmentation design and routing.

[BibT_eX]

[DOI]

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

Noise-aware buffer planning for interconnect-driven floorplanning.

[BibT_eX]

[DOI]

Katherine Shu-Min Li

Yih-Huai Cherng

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

Simultaneous floorplanning and buffer block planning.

[BibT_eX]

[DOI]

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002

Simultaneous Buffer-sizing and Wire-sizing for Clock Trees Based on Lagrangian Relaxation.

[BibT_eX]

[DOI]

Yu-Min Lee

Charlie Chung-Ping Chen

Martin D. F. Wong

VLSI Design, 2002

Arbitrarily shaped rectilinear module placement using the transitive closure graph representation.

[BibT_eX]

[DOI]

Hsin-Lung Chen

IEEE Trans. Very Large Scale Integr. Syst., 2002

Performance-driven placement for dynamically reconfigurable FPGAs.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2002

Comment on Generic Universal Switch Blocks.

[BibT_eX]

[DOI]

Hongbing Fan

Yu-Liang Wu

IEEE Trans. Computers, 2002

Formulae for Performance Optimization and Their Applications to Interconnect-Driven Floorplanning.

[BibT_eX]

[DOI]

Nicholas Chia-Yuan Chang

Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

A novel framework for multilevel routing considering routability and performance.

[BibT_eX]

[DOI]

Shih-Ping Lin

Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Arbitrary Convex and Concave Rectilinear Module Packing Using TCG.

[BibT_eX]

[DOI]

Hsin-Lung Chen

Proceedings of the 2002 Design, 2002

2001

Generic ILP-based approaches for time-multiplexed FPGA partitioning.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Matching-based algorithm for FPGA channel segmentation design.

[BibT_eX]

[DOI]

Martin D. F. Wong

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Generic ILP-Based Approaches for Dynamically Reconfigurable FPGA Partitioning.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

An Algorithm for Dynamically Reconfigurable FPGA Placement.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

Performance Optimization By Wire and Buffer Sizing Under The Transmission Line Model.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

TCG: A Transitive Closure Graph-Based Representation for Non-Slicing Floorplans.

[BibT_eX]

[DOI]

Proceedings of the 38th Design Automation Conference, 2001

2000

Timing-driven routing for symmetrical array-based FPGAs.

[BibT_eX]

[DOI]

Kai Zhu

ACM Trans. Design Autom. Electr. Syst., 2000

Crosstalk-driven interconnect optimization by simultaneous gate andwire sizing.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Generic Universal Switch Blocks.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2000

Optimal reliable crosstalk-driven interconnect optimization.

[BibT_eX]

[DOI]

Proceedings of the 2000 International Symposium on Physical Design, 2000

Rectilinear Block Placement Using B*-Trees.

[BibT_eX]

[DOI]

Yun-Chih Chang

Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

Crosstalk-Constrained Performance Optimization by Using Wire Sizing and Perturbation.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

B*-Trees: a new representation for non-slicing floorplans.

[BibT_eX]

[DOI]

Proceedings of the 37th Conference on Design Automation, 2000

An architecture-driven metric for simultaneous placement and global routing for FPGAs.

[BibT_eX]

[DOI]

Yu-Tsang Chang

Proceedings of the 37th Conference on Design Automation, 2000

1999

Quasi-Universal Switch Matrices for FPD Design.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1999

A clustering- and probability-based approach for time-multiplexed FPGA partitioning.

[BibT_eX]

[DOI]

Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Universal Switch Blocks for Three-Dimensional FPGA Design.

[BibT_eX]

[DOI]

Michael Shyu

Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, 1999

Noise-Constrained Performance Optimization by Simultaneous Gate and Wire Sizing Based on Lagrangian Relaxation.

[BibT_eX]

[DOI]

Proceedings of the 36th Conference on Design Automation, 1999

1998

Switch-matrix architecture and routing for FPDs.

[BibT_eX]

[DOI]

Proceedings of the 1998 International Symposium on Physical Design, 1998

Graph matching-based algorithms for FPGA segmentation design.

[BibT_eX]

[DOI]

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

1997

Algorithms for an FPGA switch module routing problem with application to global routing.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

1996

Universal switch modules for FPGA design.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 1996

Universal Switch-Module Design for Symmetric-Array-Based FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 1996 Fourth International Symposium on Field Programmable Gate Arrays, 1996

Fast Performance-Driven Optimization for Buffered Clock Trees Based on Lagrangian Relaxation.

[BibT_eX]

[DOI]

Chung-Ping Chen

Proceedings of the 33st Conference on Design Automation, 1996

1995

Design and analysis of FPGA/FPIC switch modules.

[BibT_eX]

[DOI]

Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

FPGA global routing based on a new congestion metric.

[BibT_eX]

[DOI]

Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

1994

A new global routing algorithm for FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

1993

Switch module design with application to two-dimensional segmentation design.

[BibT_eX]

[DOI]

Kai Zhu