Yao-Wen Chang

According to our database1, Yao-Wen Chang authored at least 280 papers between 1993 and 2020.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

Homepages:

On csauthors.net:

Bibliography

2020
Study of the Walk-Out Effect of Junction Breakdown Instability of the High-Voltage Depletion-Mode N-Channel MOSFET for NAND Flash Peripheral Device and an Efficient Layout Solution.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

Unified Redistribution Layer Routing for 2.5D IC Packages.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory.
IEEE Trans. Very Large Scale Integr. Syst., 2019

DSA-Compliant Routing for 2-D Patterns Using Block Copolymer Lithography.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Multiview Contouring for Breast Tumor on Magnetic Resonance Imaging.
J. Digit. Imaging, 2019

Analytical Mixed-Cell-Height Legalization Considering Average and Maximum Movement Minimization.
Proceedings of the 2019 International Symposium on Physical Design, 2019

Graph- and ILP-Based Cut Redistribution for Two-Dimensional Directed Self-Assembly.
Proceedings of the International Conference on Computer-Aided Design, 2019

Timing-Aware Fill Insertions with Design-Rule and Density Constraints.
Proceedings of the International Conference on Computer-Aided Design, 2019

Analytical Placement with 3D Poisson's Equation and ADMM Based Optimization for Large-Scale 2.5D Heterogeneous FPGAs.
Proceedings of the International Conference on Computer-Aided Design, 2019

Obstacle-Aware Group-Based Length-Matching Routing for Pre-Assignment Area-I/O Flip-Chip Designs.
Proceedings of the International Conference on Computer-Aided Design, 2019

BiG: A Bivariate Gradient-Based Wirelength Model for Analytical Circuit Placement.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

A DAG-Based Algorithm for Obstacle-Aware Topology-Matching On-Track Bus Routing.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

MDP-trees: multi-domain macro placement for ultra large-scale mixed-size designs.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018
Provably Good Max-Min-<i>m</i>-Neighbor-TSP-Based Subfield Scheduling for Electron-Beam Photomask Fabrication.
IEEE Trans. Very Large Scale Integr. Syst., 2018

NTUplace4dr: A Detailed-Routing-Driven Placer for Mixed-Size Circuit Designs With Technology and Region Constraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Mixed-cell-height legalization considering technology and region constraints.
Proceedings of the International Conference on Computer-Aided Design, 2018

Analytical solution of Poisson's equation and its application to VLSI global placement.
Proceedings of the International Conference on Computer-Aided Design, 2018

Mixed-cell-height placement considering drain-to-drain abutment.
Proceedings of the International Conference on Computer-Aided Design, 2018

A multithreaded initial detailed routing algorithm considering global routing guides.
Proceedings of the International Conference on Computer-Aided Design, 2018

Mixed-cell-height placement with complex minimum-implant-area constraints.
Proceedings of the International Conference on Computer-Aided Design, 2018

Novel proximal group ADMM for placement considering fogging and proximity effects.
Proceedings of the International Conference on Computer-Aided Design, 2018

Simultaneous partitioning and signals grouping for time-division multiplexing in 2.5D FPGA-based systems.
Proceedings of the International Conference on Computer-Aided Design, 2018

Generalized augmented lagrangian and its applications to VLSI global placement.
Proceedings of the 55th Annual Design Automation Conference, 2018

DSA-friendly detailed routing considering double patterning and DSA template assignments.
Proceedings of the 55th Annual Design Automation Conference, 2018

Efficient multi-layer obstacle-avoiding region-to-region rectilinear steiner tree construction.
Proceedings of the 55th Annual Design Automation Conference, 2018

WB-trees: a meshed tree representation for FinFET analog layout designs.
Proceedings of the 55th Annual Design Automation Conference, 2018

2017
Editorial.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Nanowire-Aware Routing Considering High Cut Mask Complexity.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Cut Redistribution With Directed-Self-Assembly Templates for Advanced 1-D Gridded Layouts.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

An Interview With Professor Chenming Hu, Father of 3D Transistors.
IEEE Des. Test, 2017

Generalized Force Directed Relaxation with Optimal Regions and Its Applications to Circuit Placement.
Proceedings of the 2017 ACM on International Symposium on Physical Design, 2017

Blockage-aware terminal propagation for placement wirelength minimization.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Mixed-cell-height detailed placement considering complex minimum-implant-area constraints.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Redistribution layer routing for wafer-level integrated fan-out package-on-packages.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Clock-aware placement for large-scale heterogeneous FPGAs.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

An integrated-spreading-based macro-refining algorithm for large-scale mixed-size circuit designs.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

FPGA placement and routing.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

A novel damped-wave framework for macro placement.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Detailed Placement for Two-Dimensional Directed Self-Assembly Technology.
Proceedings of the 54th Annual Design Automation Conference, 2017

Graph-Based Logic Bit Slicing for Datapath-Aware Placement.
Proceedings of the 54th Annual Design Automation Conference, 2017

Fogging Effect Aware Placement in Electron Beam Lithography.
Proceedings of the 54th Annual Design Automation Conference, 2017

Toward Optimal Legalization for Mixed-Cell-Height Circuit Designs.
Proceedings of the 54th Annual Design Automation Conference, 2017

An effective legalization algorithm for mixed-cell-height standard cells.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
Fast Lithographic Mask Optimization Considering Process Variation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Layout-Dependent Effects-Aware Analytical Analog Placement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Overlay-Aware Detailed Routing for Self-Aligned Double Patterning Lithography Using the Cut Process.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Simultaneous EUV Flare Variation Minimization and CMP Control by Coupling-Aware Dummification.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Double-Patterning Aware DSA Template Guided Cut Redistribution for Advanced 1-D Gridded Designs.
Proceedings of the 2016 on International Symposium on Physical Design, 2016

DSA-compliant routing for two-dimensional patterns using block copolymer lithography.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

VCR: simultaneous via-template and cut-template-aware routing for directed self-assembly technology.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Redistribution layer routing for integrated fan-out wafer-level chip-scale packages.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

QB-trees: towards an optimal topological representation and its applications to analog layout designs.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Minimum-implant-area-aware detailed placement with spacing constraints.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Timing-driven cell placement optimization for early slack histogram compression.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Recent research development and new challenges in analog layout synthesis.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

Circular-contour-based obstacle-aware macro placement.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
Stitch-Aware Routing for Multiple E-Beam Lithography.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Coupling-Aware Length-Ratio-Matching Routing for Capacitor Arrays in Analog Integrated Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Provably Good Max-Min-m-neighbor-TSP-Based Subfield Scheduling for Electron-Beam Photomask Fabrication.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Detailed-Routability-Driven Analytical Placement for Mixed-Size Designs with Technology and Region Constraints.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Cutting structure-aware analog placement based on self-aligned double patterning with e-beam lithography.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Routing-architecture-aware analytical placement for heterogeneous FPGAs.
Proceedings of the 52nd Annual Design Automation Conference, 2015

EUV and e-beam manufacturability: challenges and solutions.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Detailed-Routing-Driven analytical standard-cell placement.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

Non-stitch triple patterning-aware routing based on conflict graph pre-coloring.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

Layout decomposition for Spacer-is-Metal (SIM) self-aligned double patterning.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Nonuniform Multilevel Analog Routing With Matching Constraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

NTUplace4h: A Novel Routability-Driven Placement Algorithm for Hierarchical Mixed-Size Circuit Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Obstacle-Avoiding Free-Assignment Routing for Flip-Chip Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

A Novel Layout Decomposition Algorithm for Triple Patterning Lithography.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Buffered clock tree synthesis considering self-heating effects.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

Design and Implementation of a RESTful Notification Service.
Proceedings of the Intelligent Systems and Applications, 2014

Simultaneous EUV flare- and CMP-aware placement.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

Efficient and effective packing and analytical placement for large-scale heterogeneous FPGAs.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Simultaneous EUV Flare Variation Minimization and CMP Control with Coupling-Aware Dummification.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

A New Asynchronous Pipeline Template for Power and Performance Optimization.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Routability-Driven Blockage-Aware Macro Placement.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Functional ECO Using Metal-Configurable Gate-Array Spare Cells.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013
TSV-Aware Analytical Placement for 3-D IC Designs Based on a Novel Weighted-Average Wirelength Model.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Escape Routing for Staggered-Pin-Array PCBs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Graph-Based Subfield Scheduling for Electron-Beam Photomask Fabrication.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

ECO Optimization Using Metal-Configurable Gate-Array Spare Cells.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Circuit placement challenges: technical perspective.
Commun. ACM, 2013

Simultaneous OPC- and CMP-aware routing based on accurate closed-form modeling.
Proceedings of the International Symposium on Physical Design, 2013

Simultaneous analog placement and routing with current flow and current density considerations.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

An efficient and effective analytical placer for FPGAs.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Routability-driven placement for hierarchical mixed-size circuit designs.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Multiple chip planning for chip-interposer codesign.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Double patterning lithography-aware analog placement.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Symmetrical buffered clock-tree synthesis with supply-voltage alignment.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

Layer minimization in escape routing for staggered-pin-array PCBs.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
Fast Timing-Model Independent Buffered Clock-Tree Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

An Efficient Pre-Assignment Routing Algorithm for Flip-Chip Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Unified Analytical Global Placement for Large-Scale Mixed-Size Circuit Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

TRECO: Dynamic Technology Remapping for Timing Engineering Change Orders.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Native-Conflict and Stitch-Aware Wire Perturbation for Double Patterning Technology.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Timing ECO Optimization Via Bézier Curve Smoothing and Fixability Identification.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Statistical thermal modeling and optimization considering leakage power variations.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Non-uniform multilevel analog routing with matching constraints.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Obstacle-avoiding free-assignment routing for flip-chip designs.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

A chip-package-board co-design methodology.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Simultaneous flare level and flare variation minimization with dummification in EUVL.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Structure-aware placement for datapath-intensive circuit designs.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Timing ECO optimization using metal-configurable gate-array spare cells.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011
Guest Editorial.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Thermal-Driven Analog Placement Considering Device Matching.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Cross-Contamination Aware Design Methodology for Pin-Constrained Digital Microfluidic Biochips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Simultaneous Layout Migration and Decomposition for Double Patterning Technology.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Voltage-Drop Aware Analytical Placement by Global Power Spreading for Mixed-Size Circuit Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Pulsed-Latch Aware Placement for Timing-Integrity Optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

A SAT-based routing algorithm for cross-referencing biochips.
Proceedings of the 2011 International Workshop on System Level Interconnect Prediction, 2011

A corner stitching compliant B<sup>∗</sup>-tree representation and its applications to analog placement.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Routability-driven analytical placement for mixed-size circuit designs.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

PRICE: Power reduction by placement and clock-network co-synthesis for pulsed-latch designs.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Heterogeneous B<sup>∗</sup>-trees for analog placement with symmetry and regularity considerations.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

TSV-aware analytical placement for 3D IC designs.
Proceedings of the 48th Design Automation Conference, 2011

Simultaneous functional and timing ECO.
Proceedings of the 48th Design Automation Conference, 2011

2010
ILP-Based Pin-Count Aware Design Methodology for Microfluidic Biochips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Multilayer Global Routing With Via and Wire Capacity Considerations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

ECO Timing Optimization Using Spare Cells and Technology Remapping.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Area-I/O Flip-Chip Routing for Chip-Package Co-Design Considering Signal Skews.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Predictive Formulae for OPC With Applications to Lithography-Friendly Routing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Design of an Omnidirectional Multibeam Transmitter for High-Speed Indoor Wireless Communications.
EURASIP J. Wirel. Commun. Netw., 2010

Density gradient minimization with coupling-constrained dummy fill for CMP control.
Proceedings of the 2010 International Symposium on Physical Design, 2010

Efficient provably good OPC modeling and its applications to interconnect optimization.
Proceedings of the 28th International Conference on Computer Design, 2010

High variation-tolerant obstacle-avoiding clock mesh synthesis with symmetrical driving trees.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Recent research development in flip-chip routing.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Template-mask design methodology for double patterning technology.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Redundant-wires-aware ECO timing and mask cost optimization.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Design-hierarchy aware mixed-size placement for routability optimization.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Native-conflict-aware wire perturbation for double patterning technology.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Blockage-avoiding buffered clock-tree synthesis for clock latency-range and skew minimization.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

Three-dimensional integrated circuits (3D IC) floorplan and power/ground network co-synthesis.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
T-trees: A tree-based representation for temporal and three-dimensional floorplanning.
ACM Trans. Design Autom. Electr. Syst., 2009

A Progressive-ILP-Based Routing Algorithm for the Synthesis of Cross-Referencing Biochips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Analog Placement Based on Symmetry-Island Formulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Voltage-Island Partitioning and Floorplanning Under Timing Constraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

An Integer-Linear-Programming-Based Routing Algorithm for Flip-Chip Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

A Novel Wire-Density-Driven Full-Chip Routing System for CMP Variation Control.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Essential Issues in Analytical Placement Algorithms.
IPSJ Trans. System LSI Design Methodology, 2009

Post-floorplanning power/ground ring synthesis for multiple-supply-voltage designs.
Proceedings of the 2009 International Symposium on Physical Design, 2009

BIST design optimization for large-scale embedded memory cores.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Spare-cell-aware multilevel analytical placement.
Proceedings of the 46th Design Automation Conference, 2009

Flip-chip routing with unified area-I/O pad assignments for package-board co-design.
Proceedings of the 46th Design Automation Conference, 2009

High-performance global routing with fast overflow reduction.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
Global Interconnect Planning.
Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

Packing Floorplan Representations.
Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

BioRoute: A Network-Flow-Based Routing Algorithm for the Synthesis of Digital Microfluidic Biochips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

An Efficient Graph-Based Algorithm for ESD Current Path Analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Multilayer Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Spanning Graphs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Spanning Graphs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

An Optimal Network-Flow-Based Simultaneous Diode and Jumper Insertion Algorithm for Antenna Fixing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

MP-Trees: A Packing-Based Macro Placement Algorithm for Modern Mixed-Size Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs With Preplaced Blocks and Density Constraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Metal-Density-Driven Placement for CMP Variation and Routability.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

A New Multilevel Framework for Large-Scale Interconnect-Driven Floorplanning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Full-Chip Routing Considering Double-Via Insertion.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Effective Wire Models for X-Architecture Placement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Multi-layer global routing considering via and wire capacities.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Routing for chip-package-board co-design considering differential pairs.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Area-I/O flip-chip routing for chip-package co-design.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Constraint graph-based macro placement for modern mixed-size circuit designs.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

A progressive-ILP based routing algorithm for cross-referencing biochips.
Proceedings of the 45th Design Automation Conference, 2008

Routability-driven analytical placement by net overlapping removal for large-scale mixed-size designs.
Proceedings of the 45th Design Automation Conference, 2008

2007
Temporal floorplanning using the three-dimensional transitive closure subGraph.
ACM Trans. Design Autom. Electr. Syst., 2007

An Exact Jumper-Insertion Algorithm for Antenna Violation Avoidance/Fixing Considering Routing Obstacles.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

An Optimal Jumper-Insertion Algorithm for Antenna Avoidance/Fixing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Power/Ground Network and Floorplan Cosynthesis for Fast Design Convergence.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Multilevel Full-Chip Routing With Testability and Yield Enhancement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

MB<sup>ast</sup>-Tree: A Multilevel Floorplanner for Large-Scale Building-Module Design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

A Network-Flow-Based RDL Routing Algorithmz for Flip-Chip Design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Multilevel Full-Chip Gridless Routing With Applications to Optical-Proximity Correction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Placement of defect-tolerant digital microfluidic biochips using the T-tree formulation.
ACM J. Emerg. Technol. Comput. Syst., 2007

X-Route: An X-architecture full-chip multilevel router.
Proceedings of the 2007 IEEE International SOC Conference, 2007

Statistical circuit optimization considering device andinterconnect process variations.
Proceedings of the Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), 2007

A Statistical Approach to the Timing-Yield Optimization of Pipeline Circuits.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

Efficient obstacle-avoiding rectilinear steiner tree construction.
Proceedings of the 2007 International Symposium on Physical Design, 2007

X-architecture placement based on effective wire models.
Proceedings of the 2007 International Symposium on Physical Design, 2007

Post-placement leakage optimization for partially dynamically reconfigurable FPGAs.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

3D Video Applications and Intelligent Video Surveillance Camera and its VLSI Design.
Proceedings of the 2007 IEEE International Conference on Multimedia and Expo, 2007

BioRoute: a network-flow based routing algorithm for digital microfluidic biochips.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Efficient multi-layer obstacle-avoiding rectilinear Steiner tree construction.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

An efficient algorithm for statistical circuit optimization using Lagrangian relaxation.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

An ILP algorithm for post-floorplanning voltage-island generation considering power-network planning.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

ECO timing optimization using spare cells.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Novel wire density driven full-chip routing for CMP variation control.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

A Provably Good Approximation Algorithm for Power Optimization Using Multiple Supply Voltages.
Proceedings of the 44th Design Automation Conference, 2007

An Integer Linear Programming Based Routing Algorithm for Flip-Chip Design.
Proceedings of the 44th Design Automation Conference, 2007

MP-trees: A Packing-Based Macro Placement Algorithm for Mixed-Size Designs.
Proceedings of the 44th Design Automation Conference, 2007

Recent Research and Emerging Challenges in Physical Design for Manufacturability/Reliability.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs.
Proceedings of the Modern Circuit Placement, Best Practices and Results, 2007

Full-Chip Nanometer Routing Techniques.
Analog Circuits and Signal Processing, Springer, ISBN: 978-1-4020-6194-3, 2007

2006
Reliable crosstalk-driven interconnect optimization.
ACM Trans. Design Autom. Electr. Syst., 2006

RLC Coupling-Aware Simulation and On-Chip Bus Encoding for Delay Reduction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

IEEE Standard 1500 Compatible Interconnect Diagnosis for Delay and Crosstalk Faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Modern Floorplanning Based on B<sup>*</sup>-Tree and Fast Simulated Annealing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Multilevel routing with jumper insertion for antenna avoidance.
Integr., 2006

An optimal jumper insertion algorithm for antenna avoidance/fixing on general routing trees with obstacles.
Proceedings of the 2006 International Symposium on Physical Design, 2006

Floorplan and power/ground network co-synthesis for fast design convergence.
Proceedings of the 2006 International Symposium on Physical Design, 2006

NTUplace2: a hybrid placer using partitioning and analytical techniques.
Proceedings of the 2006 International Symposium on Physical Design, 2006

Inductance extraction for general interconnect structures.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Current path analysis for electrostatic discharge protection.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Voltage island aware floorplanning for power and timing optimization.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

An optimal simultaneous diode/jumper insertion algorithm for antenna fixing.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

A high-quality mixed-size analytical placer considering preplaced blocks and density constraints.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Placement of digital microfluidic biochips using the t-tree formulation.
Proceedings of the 43rd Design Automation Conference, 2006

Novel full-chip gridless routing considering double-via insertion.
Proceedings of the 43rd Design Automation Conference, 2006

Simultaneous block and I/O buffer floorplanning for flip-chip design.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

A novel framework for multilevel full-chip gridless routing.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
TCG: A transitive closure graph-based representation for general floorplans.
IEEE Trans. Very Large Scale Integr. Syst., 2005

Crosstalk- and performance-driven multilevel full-chip routing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Reconfigurable Platform for Content Science Research.
Proceedings of the 11th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2005), 2005

NTUplace: a ratio partitioning based placement algorithm for large-scale mixed-size designs.
Proceedings of the 2005 International Symposium on Physical Design, 2005

Modern floorplanning based on fast simulated annealing.
Proceedings of the 2005 International Symposium on Physical Design, 2005

Joint exploration of architectural and physical design spaces with thermal consideration.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

RLC coupling-aware simulation for on-chip buses and their encoding for delay reduction.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A routing algorithm for flip-chip design.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

IMF: interconnect-driven multilevel floorplanning for large-scale building-module designs.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

An exact jumper insertion algorithm for antenna effect avoidance/fixing.
Proceedings of the 42nd Design Automation Conference, 2005

Multilevel full-chip routing for the X-based architecture.
Proceedings of the 42nd Design Automation Conference, 2005

SoC test scheduling using the B-tree based floorplanning technique.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Placement with symmetry constraints for analog layout design using TCG-S.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Multilevel full-chip gridless routing considering optical proximity correction.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Timing modeling and optimization under the transmission line model.
IEEE Trans. Very Large Scale Integr. Syst., 2004

TCG-S: orthogonal coupling of P/sup */-admissible representations for general floorplans.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Simultaneous floor plan and buffer-block optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

MR: a new framework for multilevel full-chip routing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

A clustering- and probability-based approach for time-multiplexed FPGA partitioning.
Integr., 2004

Multilevel routing with antenna avoidance.
Proceedings of the 2004 International Symposium on Physical Design, 2004

RLC effects on worst-case switching pattern for on-chip buses.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Placement with Alignment and Performance Constraints Using the B*-Tree Representation.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

Temporal floorplanning using the T-tree formulation.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Efficient power/ground network analysis for power integrity-driven design methodology.
Proceedings of the 41th Design Automation Conference, 2004

Temporal floorplanning using 3D-subTCG.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

Layout techniques for on-chip interconnect inductance reduction.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

Integrating buffer planning with floorplanning for simultaneous multi-objective optimization.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003
Corner sequence - a P-admissible floorplan representation with a worst case linear-time packing scheme.
IEEE Trans. Very Large Scale Integr. Syst., 2003

Rectilinear block placement using B<sup>*</sup>-trees.
ACM Trans. Design Autom. Electr. Syst., 2003

Analysis of FPGA/FPIC switch modules.
ACM Trans. Design Autom. Electr. Syst., 2003

A Fast Crosstalk- and Performance-Driven Multilevel Routing System.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Multilevel floorplanning/placement for large-scale modules using B*-trees.
Proceedings of the 40th Design Automation Conference, 2003

Graph matching-based algorithms for array-based FPGA segmentation design and routing.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

Noise-aware buffer planning for interconnect-driven floorplanning.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

Simultaneous floorplanning and buffer block planning.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
Simultaneous Buffer-sizing and Wire-sizing for Clock Trees Based on Lagrangian Relaxation.
VLSI Design, 2002

Arbitrarily shaped rectilinear module placement using the transitive closure graph representation.
IEEE Trans. Very Large Scale Integr. Syst., 2002

Performance-driven placement for dynamically reconfigurable FPGAs.
ACM Trans. Design Autom. Electr. Syst., 2002

Comment on Generic Universal Switch Blocks.
IEEE Trans. Computers, 2002

Formulae for Performance Optimization and Their Applications to Interconnect-Driven Floorplanning.
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

A novel framework for multilevel routing considering routability and performance.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Arbitrary Convex and Concave Rectilinear Module Packing Using TCG.
Proceedings of the 2002 Design, 2002

TCG-S: orthogonal coupling of P<sup>*</sup>-admissible representations for general floorplans.
Proceedings of the 39th Design Automation Conference, 2002

2001
Generic ILP-based approaches for time-multiplexed FPGA partitioning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Matching-based algorithm for FPGA channel segmentation design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Generic ILP-Based Approaches for Dynamically Reconfigurable FPGA Partitioning.
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

An Algorithm for Dynamically Reconfigurable FPGA Placement.
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

Performance Optimization By Wire and Buffer Sizing Under The Transmission Line Model.
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

TCG: A Transitive Closure Graph-Based Representation for Non-Slicing Floorplans.
Proceedings of the 38th Design Automation Conference, 2001

2000
Timing-driven routing for symmetrical array-based FPGAs.
ACM Trans. Design Autom. Electr. Syst., 2000

Crosstalk-driven interconnect optimization by simultaneous gate andwire sizing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Generic Universal Switch Blocks.
IEEE Trans. Computers, 2000

Optimal reliable crosstalk-driven interconnect optimization.
Proceedings of the 2000 International Symposium on Physical Design, 2000

Rectilinear Block Placement Using B*-Trees.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

Crosstalk-Constrained Performance Optimization by Using Wire Sizing and Perturbation.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

B*-Trees: a new representation for non-slicing floorplans.
Proceedings of the 37th Conference on Design Automation, 2000

An architecture-driven metric for simultaneous placement and global routing for FPGAs.
Proceedings of the 37th Conference on Design Automation, 2000

1999
Quasi-Universal Switch Matrices for FPD Design.
IEEE Trans. Computers, 1999

A clustering- and probability-based approach for time-multiplexed FPGA partitioning.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Universal Switch Blocks for Three-Dimensional FPGA Design.
Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, 1999

Noise-Constrained Performance Optimization by Simultaneous Gate and Wire Sizing Based on Lagrangian Relaxation.
Proceedings of the 36th Conference on Design Automation, 1999

1998
Switch-matrix architecture and routing for FPDs.
Proceedings of the 1998 International Symposium on Physical Design, 1998

Graph matching-based algorithms for FPGA segmentation design.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

1997
Algorithms for an FPGA switch module routing problem with application to global routing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

1996
Universal switch modules for FPGA design.
ACM Trans. Design Autom. Electr. Syst., 1996

Universal Switch-Module Design for Symmetric-Array-Based FPGAs.
Proceedings of the 1996 Fourth International Symposium on Field Programmable Gate Arrays, 1996

Fast Performance-Driven Optimization for Buffered Clock Trees Based on Lagrangian Relaxation.
Proceedings of the 33st Conference on Design Automation, 1996

1995
Design and analysis of FPGA/FPIC switch modules.
Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

FPGA global routing based on a new congestion metric.
Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

1994
A new global routing algorithm for FPGAs.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

1993
Switch module design with application to two-dimensional segmentation design.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993


  Loading...