Horst A. Gieser

According to our database, Horst A. Gieser authored at least 13 papers between 2003 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2022

Physical and Functional Reverse Engineering Challenges for Advanced Semiconductor Solutions.

Bernhard Lippmann, Ann-Christin Bette, Matthias Ludwig, Johannes Mutter, Johanna Baehr, Alexander Hepp, Horst A. Gieser, Nicola Kovac, Tobias Zweifel, Martin Rasche, Oliver Kellermann

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2020

Investigating Profiled Side-Channel Attacks Against the DES Key Schedule.

Johann Heyszl, Katja Miller, Florian Unterstein, Marc Schink, Alexander Wagner, Horst A. Gieser, Sven Freud, Tobias Damm, Dominik Klein, Dennis Kügler

IACR Trans. Cryptogr. Hardw. Embed. Syst., 2020

Verification of physical designs using an integrated reverse engineering flow for nanoscale technologies.

Bernhard Lippmann, Niklas Unverricht, Aayush Singla, Matthias Ludwig, Michael Werner, Peter Egger, Anja Dübotzky, Helmut Gräb, Horst A. Gieser, Martin Rasche, Oliver Kellermann

Integr., 2020

2019

Integrated flow for reverse engineering of nanoscale technologies.

Bernhard Lippmann, Michael Werner, Niklas Unverricht, Aayush Singla, Peter Egger, Anja Dübotzky, Horst A. Gieser, Martin Rasche, Oliver Kellermann, Helmut Graeb

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2015

Electrostatic discharge sensitivity investigation on organic field-effect thin film transistors.

Tekfouy Lim, Horst A. Gieser, Luca Santarelli, Franco Cacialli

Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

2009

Investigating the CDM susceptibility of IC's at package and wafer level by capacitive coupled TLP.

Heinrich Wolf, Horst A. Gieser, Dirk Walter

Microelectron. Reliab., 2009

2006

ESD Susceptibility of Submicron Air Gaps.

Heinrich Wolf, Horst A. Gieser, Detlef Bonfert, Markus Hauser

Microelectron. Reliab., 2006

Study of CDM specific effects for a smart power input protection structure.

M. Etherton, Ning Qu, J. Willemen, Wolfgang Wilkening, S. Mettler, Mariano Dissegna, R. Stella, L. Zullino, A. Andreini, Horst A. Gieser

Microelectron. Reliab., 2006

Transient-induced latch-up test setup for wafer-level and package-level.

Detlef Bonfert, Horst A. Gieser, Heinrich Wolf, M. Frank, A. Konrad, J. Schulz

Microelectron. Reliab., 2006

2005

Capacitively coupled transmission line pulsing cc-TLP--a traceable and reproducible stress method in the CDM-domain.

Heinrich Wolf, Horst A. Gieser, Wolfgang Stadler, Wolfgang Wilkening

Microelectron. Reliab., 2005

A Dedicated TLP Set-Up to Investigate the ESD Robustness of RF Elements and Circuits.

Heinrich Wolf, Horst A. Gieser, Wolfgang Soldner, Harald Gossner

Microelectron. Reliab., 2005

Transient latch-up: experimental analysis and device simulation.

S. Bargstädt-Franke, Wolfgang Stadler, Kai Esmark, Martin Streibl, Krzysztof Domanski, Horst A. Gieser, Heinrich Wolf, Waclaw Bala

Microelectron. Reliab., 2005

2003

On-chip electrostatic discharge ESD.

Horst A. Gieser

Microelectron. Reliab., 2003