Hossein Ghasemian

According to our database, Hossein Ghasemian authored at least 8 papers between 2018 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2023

High Efficient GDI-CNTFET-Based Approximate Full Adder for Next Generation of Computer Architectures.

Ayoub Sadeghi, Razieh Ghasemi, Hossein Ghasemian, Nabiollah Shiri

IEEE Embed. Syst. Lett., March, 2023

Efficient and optimized approximate GDI full adders based on dynamic threshold CNTFETs for specific least significant bits.

Ayoub Sadeghi, Razieh Ghasemi, Hossein Ghasemian, Nabiollah Shiri

Frontiers Inf. Technol. Electron. Eng., 2023

2021

Design of a Low Power Analog and Multi-shaped Fully Programmable Twin-Cell Membership Function Generator Circuit in 65 nm CMOS Technology.

Hossein Ghasemian, Saeed Karami, Ebrahim Abiri, Mohammad Reza Salehi

Circuits Syst. Signal Process., 2021

A New Low-Power Charge Pump with a Glitch-Free PFD for Speedup the Acquisition Process of a PLL in 65 nm CMOS Technology.

Hossein Ghasemian, Amin Bahrami, Ebrahim Abiri, Mohammad Reza Salehi

Circuits Syst. Signal Process., 2021

2020

An implementation of a new 11-bit 1.2 ​GS/s hybrid DAC with a noval 3-bit Sub-DAC.

Hossein Ghasemian, Amirhossein Ahmadi, Ebrahim Abiri, Mohammad Reza Salehi

Microelectron. J., 2020

2019

A novel high-speed low-power dynamic comparator with complementary differential input in 65 nm CMOS technology.

Hossein Ghasemian, Razieh Ghasemi, Ebrahim Abiri, Mohammad Reza Salehi

Microelectron. J., 2019

2018

A Two Stage Variable-Gain Low-Noise Amplifier for X-Band in 0.18 µm CMOS.

Mohammad Reza Nikbakhsh, Ebrahim Abiri, Hossein Ghasemian, Mohammad Reza Salehi

Wirel. Pers. Commun., 2018

Two-stage current-reused variable-gain low-noise amplifier for X-band receivers in 65 nm complementary metal oxide semiconductor technology.

Mohammad Reza Nikbakhsh, Ebrahim Abiri, Hossein Ghasemian, Mohammad Reza Salehi

IET Circuits Devices Syst., 2018