Hsiao-Han Hou

According to our database, Hsiao-Han Hou authored at least 2 papers between 2010 and 2013.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

2013

A 800 Mbps and 12.37 ps Jitter Bidirectional Mixed-Voltage I/O Buffer With Dual-Path Gate-Tracking Circuit.

Chua-Chin Wang, Chih-Lin Chen, Hsin-Yuan Tseng, Hsiao-Han Hou, Chun-Ying Juan

IEEE Trans. Circuits Syst. I Regul. Pap., 2013

2010

A PCI166-compatible 3×VDD-tolerant mixed-voltage I/O buffer.

Ron-Chi Kuo, Hsiao-Han Hou, Chua-Chin Wang

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010