Hsin-Yuan Tseng

According to our database, Hsin-Yuan Tseng authored at least 7 papers between 2012 and 2015.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

2015

Process corner detection by skew inverters for 500 MHZ 2×VDD output buffer using 40-nm CMOS technology.

Chua-Chin Wang, Wen-Je Lu, Kai-Wei Juan, Wei Lin, Hsin-Yuan Tseng, Chun-Ying Juan

Microelectron. J., 2015

2013

A 800 Mbps and 12.37 ps Jitter Bidirectional Mixed-Voltage I/O Buffer With Dual-Path Gate-Tracking Circuit.

Chua-Chin Wang, Chih-Lin Chen, Hsin-Yuan Tseng, Hsiao-Han Hou, Chun-Ying Juan

IEEE Trans. Circuits Syst. I Regul. Pap., 2013

On-Chip Process and Temperature Monitor for Self-Adjusting Slew Rate Control of 2, ×, VDD Output Buffers.

Chua-Chin Wang, Chih-Lin Chen, Ron-Chi Kuo, Hsin-Yuan Tseng, Jen-Wei Liu, Chun-Ying Juan

IEEE Trans. Circuits Syst. I Regul. Pap., 2013

A 2×VDD output buffer with PVT detector for slew rate compensation.

Chua-Chin Wang, Wen-Je Lu, Chih-Lin Chen, Hsin-Yuan Tseng, Ron-Chi Kuo, Chun-Ying Juan

Microelectron. J., 2013

A high-speed 2×VDD output buffer with PVT detection using 40-nm CMOS technology.

Chua-Chin Wang, Wen-Je Lu, Hsin-Yuan Tseng

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012

A slew rate self-adjusting 2×VDD output buffer With PVT compensation.

Chih-Lin Chen, Hsin-Yuan Tseng, Ron-Chi Kuo, Chua-Chin Wang

Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

On-chip MOS PVT variation monitor for slew rate self-adjusting 2×VDD output buffers.

Chih-Lin Chen, Hsin-Yuan Tseng, Ron-Chi Kuo, Chua-Chin Wang

Proceedings of the IEEE International Conference on IC Design & Technology, 2012