Hsin-Che Wu

According to our database, Hsin-Che Wu authored at least 4 papers between 2022 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2025

A Power-Efficient 0.5668 TOPS/W Digital Logic Accelerator Implemented Using 40-nm CMOS Process for Underwater Object Recognition Usage.

Chua-Chin Wang, Shih-Heng Luo, Hsin-Che Wu, Ralph Gerard B. Sangalang, Chewnpu Jou, Harry Hsia, Lan-Chou Cho

IEEE Access, 2025

2024

A 54.61-GOPS 96.35-mW Digital Logic Accelerator For Underwater Object Recognition DNN Using 40-nm CMOS Process.

Chua-Chin Wang, Shih-Heng Luo, Hsin-Che Wu, Ralph Gerard B. Sangalang, Chewnpu Jou, Harry Hsia, Lan-Chou Cho

Proceedings of the 6th IEEE International Conference on AI Circuits and Systems, 2024

2022

A 40.96-GOPS 196.8-mW Digital Logic Accelerator Used in DNN for Underwater Object Recognition.

Chua-Chin Wang, Ralph Gerard B. Sangalang, Chien-Ping Kuo, Hsin-Che Wu, Yi Hsu, Shen-Fu Hsiao, Chia-Hung Yeh

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

A Power Effective DLA for PBs in Opto-Electrical Neural Network Architecture.

Ralph Gerard B. Sangalang, Shih-Heng Luo, Hsin-Che Wu, Bao-Qi He, Shen-Fu Hsiao, Chua-Chin Wang, Chewnpu Jou, Harry Hsia, Douglas C.-H. Yu

Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022