Hsin-Ta Chien

According to our database, Hsin-Ta Chien authored at least 2 papers between 2025 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2026

A Fully Analog Computing-in-Memory Macro With INT8-MAC Operations for Edge-AI Device.

Wei-Cheng Huang, Hsin-Ta Chien, Soon-Jyh Chang, Jia-Hao Hu, Chih-Hung Kuo

IEEE J. Emerg. Sel. Topics Circuits Syst., June, 2026

2025

7.1 A 212.5Gb/s DSP-Based PAM-4 Transceiver with 50dB Loss Compensation for Large AI System Interconnects in 4nm FinFET.

Ehung Chen, Henry Park, Mohammed Abdullatif, Miguel Gandara, Ahmed ElShater, Amr Khashaba, Shih-Hao Huang, Tsz-Bin Liu, Atharav Atharav, Joonyeong Lee, Qaiser Nehal, Mohamed Megahed, Yusang Chun, Cheng-En Shieh, Vidhan Jolly, SoonWon Kwon, Hsin-Ta Chien, Ke-Chung Wu, Cheng-En Liu, Peng Yan, Po-Jui Li, Chun-Han Chen, Tzu-Shun Lin, Pei-Chieh Liu, Tamer A. Ali

Proceedings of the IEEE International Solid-State Circuits Conference, 2025