Miguel Gandara

According to our database1, Miguel Gandara authored at least 9 papers between 2017 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

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Bibliography

2023
A 4.63pJ/b 112Gb/s DSP-Based PAM-4 Transceiver for a Large-Scale Switch in 5nm FinFET.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

2022
An Efficient Analog Circuit Sizing Method Based on Machine Learning Assisted Global Optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

2021
A 74.5-dB Dynamic Range 10-MHz BW CT-ΔΣ ADC With Distributed-Input VCO and Embedded Capacitive-π Network in 40-nm CMOS.
IEEE J. Solid State Circuits, 2021

56/112Gbps Wireline Transceivers for Next Generation Data Centers on 7nm FINFET CMOS Technology.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021

2020
6.2 A 460mW 112Gb/s DSP-Based Transceiver with 38dB Loss Compensation for Next-Generation Data Centers in 7nm FinFET Technology.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2018
A 13-ENOB Second-Order Noise-Shaping SAR ADC Realizing Optimized NTF Zeros Using the Error-Feedback Structure.
IEEE J. Solid State Circuits, 2018

A 13-ENOB 2<sup>nd</sup>-order noise-shaping SAR ADC realizing optimized NTF zeros using an error-feedback structure.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2017
A pipelined SAR ADC reusing the comparator as residue amplifier.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

A 172dB-FoM pipelined SAR ADC using a regenerative amplifier with self-timed gain control and mixed-signal background calibration.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017


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