Hsiu-Cheng Chang

According to our database1, Hsiu-Cheng Chang authored at least 17 papers between 2005 and 2014.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
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PhD thesis 
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Links

On csauthors.net:

Bibliography

2014
A 360-degree panoramic video system design.
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

An Adaboost-based two-level moving object detection architecture with dynamic ROI allocation.
Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2014

2013
A view scalable multi-view video decoder system.
Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

2012
High efficiency data access system architecture for deblocking filter supporting multiple video coding standards.
IEEE Trans. Consumer Electron., 2012

A two level mode decision algorithm for H.264 high profile intra encoding.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

An inter-frame/inter-view cache architecture design for multi-view video decoders.
Proceedings of the Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, 2012

2011
A dynamic quality-adjustable H.264 intra coder.
IEEE Trans. Consumer Electron., 2011

A H.264/MPEG-2 dual mode video decoder chip supporting temporal/spatial scalable video.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2009
A Dynamic Quality-Adjustable H.264 Video Encoder for Power-Aware Video Applications.
IEEE Trans. Circuits Syst. Video Technol., 2009

A High Throughput Deblocking Filter Design Supporting Multiple Video Coding Standards.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

A Dynamic Quality-scalable H.264 Video Encoder.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

A dynamic quality-scalable H.264 video encoder chip.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
A high throughput in-loop de-blocking filter supporting H.264/AVC BP/MP/HP video coding.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007
A 160K Gates/4.5 KB SRAM H.264 Video Decoder for HDTV Applications.
IEEE J. Solid State Circuits, 2007

A Quality Scalable H.264/AVC Baseline Intra Encoder for High Definition Video Applicaitons.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

A 7mW-to-183mW Dynamic Quality-Scalable H.264 Video Encoder Chip.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2005
A novel low-cost high-performance VLSI architecture for MPEG-4 AVC/H.264 CAVLC decoding.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005


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