Hsuan-Ming Chou

According to our database1, Hsuan-Ming Chou authored at least 9 papers between 2010 and 2016.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2016
High-Performance Deadlock-Free ID Assignment for Advanced Interconnect Protocols.
IEEE Trans. Very Large Scale Integr. Syst., 2016

2015
Soft-Error-Tolerant Design Methodology for Balancing Performance, Power, and Reliability.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Hybrid coverage assertions for efficient coverage analysis across simulation and emulation environments.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Concurrency-oriented SoC re-certification by reusing block-level test vectors.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

2012
A probabilistic analysis method for functional qualification under Mutation Analysis.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Post silicon skew tuning: Survey and analysis.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
Useful-skew clock optimization for multi-power mode designs.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

2010
Synthesis of an efficient controlling structure for post-silicon clock skew minimization.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

An efficient phase detector connection structure for the skew synchronization system.
Proceedings of the 47th Design Automation Conference, 2010


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