Chun-Yao Wang

Orcid: 0000-0002-4536-214X

According to our database1, Chun-Yao Wang authored at least 107 papers between 2001 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2024
IR drop Prediction Based on Machine Learning and Pattern Reduction.
Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

A Hybrid Approach to Reverse Engineering on Combinational Circuits.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023
A Constructive Approach for Threshold Function Identification.
ACM Trans. Design Autom. Electr. Syst., September, 2023

A Flexible Cluster Tool Simulation Framework with Wafer Batch Dispatching Time Recommendation.
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

Invited Paper: Overview of 2023 CAD Contest at ICCAD.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

A Robust Approach to Detecting Non-Equivalent Quantum Circuits Using Specially Designed Stimuli.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

Approximate Logic Synthesis by Genetic Algorithm with an Error Rate Guarantee.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022
LOOPLock 2.0: An Enhanced Cyclic Logic Locking Approach.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

A Don't-Care-Based Approach to Reducing the Multiplicative Complexity in Logic Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Don't Care Computation and De Morgan Transformation for Threshold Logic Network Optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Majority Logic Circuit Minimization Using Node Addition and Removal.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

An Approach to Unlocking Cyclic Logic Locking: LOOPLock 2.0.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

Overview of 2022 CAD Contest at ICCAD.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

2021
Diagnosis for Reconfigurable Single-Electron Transistor Arrays with a More Generalized Defect Model.
ACM J. Emerg. Technol. Comput. Syst., 2021

Industry 3.5 to empower smart production for poultry farming and an empirical study for broiler live weight prediction.
Comput. Ind. Eng., 2021

An IMU-aided Fitness System.
Proceedings of the 34th IEEE International System-on-Chip Conference, 2021

Cluster Tool Performance Analysis using Graph Database.
Proceedings of the 34th IEEE International System-on-Chip Conference, 2021

On Reduction of Computations for Threshold Function Identification.
Proceedings of the 34th IEEE International System-on-Chip Conference, 2021

On Synthesizing Memristor-Based Logic Circuits in Area-Constrained Crossbar Arrays.
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

Overview of 2021 CAD Contest at ICCAD.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

An Efficient Approximate Node Merging with an Error Rate Guarantee.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

A General Equivalence Checking Framework for Multivalued Logic.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020
A New Necessary Condition for Threshold Function Identification.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

LOOPLock: Logic Optimization-Based Cyclic Logic Locking.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

A Dynamic Expansion Order Algorithm for the SAT-based Minimization.
Proceedings of the 33rd IEEE International System-on-Chip Conference, 2020

IMU-based Smart Knee Pad for Walking Distance and Stride Count Measurement.
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

Rehabilitation System for Limbs using IMUs.
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

A Convolutional Result Sharing Approach for Binarized Neural Network Inference.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
Threshold Function Identification by Redundancy Removal and Comprehensive Weight Assignments.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

A Glitch Key-Gate for Logic Locking.
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

A Smart Single-Sensor Device for Instantaneously Monitoring Lower Limb Exercises.
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

2018
On Synthesizing Memristor-Based Logic Circuits With Minimal Operational Pulses.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Using range-equivalent circuits for facilitating bounded sequential equivalence checking.
Proceedings of the 2018 International Symposium on VLSI Design, 2018

Architecture Exploration and Delay Minimization Synthesis for SET-Based Programmable Gate Arrays.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

A Hybrid Approach to Equivalent Fault Identification for Verification Environment Qualification.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

Logic optimization with considering boolean relations.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Efficient synthesis of approximate threshold logic circuits with an error rate guarantee.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
Dynamic Diagnosis for Defective Reconfigurable Single-Electron Transistor Arrays.
IEEE Trans. Very Large Scale Integr. Syst., 2017

A case study on mathematical expression recognition to GPU.
J. Supercomput., 2017

In&Out: Restructuring for threshold logic network optimization.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

Majority logic circuits optimisation by node merging.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
Diagnosis and Synthesis for Defective Reconfigurable Single-Electron Transistor Arrays.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Area-Aware Decomposition for Single-Electron Transistor Arrays.
ACM Trans. Design Autom. Electr. Syst., 2016

Minimization of Number of Neurons in Voronoi Diagram-Based Artificial Neural Networks.
IEEE Trans. Multi Scale Comput. Syst., 2016

An Efficient Interpolation-Based Projected Sum of Product Decomposition via Genetic Algorithm.
J. Multiple Valued Log. Soft Comput., 2016

MajorSat: A SAT solver to majority logic.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
Synthesis for Width Minimization in the Single-Electron Transistor Array.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Correctness Analysis and Power Optimization for Probabilistic Boolean Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Synthesis and verification of cyclic combinational circuits.
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015

CSL: Coordinated and scalable logic synthesis techniques for effective NBTI reduction.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Using structural relations for checking combinationality of cyclic circuits.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

A defect-aware approach for mapping reconfigurable Single-Electron Transistor arrays.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Gait and Balance Analysis for Patients With Alzheimer's Disease Using an Inertial-Sensor-Based Wearable Instrument.
IEEE J. Biomed. Health Informatics, 2014

Alzheimer's disease classification based on gait information.
Proceedings of the 2014 International Joint Conference on Neural Networks, 2014

BDD-based synthesis of reconfigurable single-electron transistor arrays.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Width minimization in the Single-Electron Transistor array synthesis.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Rewiring for threshold logic circuit minimization.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Verification of Reconfigurable Binary Decision Diagram-Based Single-Electron Transistor Arrays.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

A Synthesis Algorithm for Reconfigurable Single-Electron Transistor Arrays.
ACM J. Emerg. Technol. Comput. Syst., 2013

Pattern generation for Mutation Analysis using Genetic Algorithms.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Sensitization criterion for threshold logic circuits and its application.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

On reconfigurable single-electron transistor arrays synthesis using reordering techniques.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
Logic Restructuring Using Node Addition and Removal.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Deco: A Decentralized, Cooperative Atomic Commit Protocol.
J. Comput. Networks Commun., 2012

Error Injection & Correction: An efficient formal logic restructuring algorithm.
Proceedings of the International SoC Design Conference, 2012

Gait analysis for patients with Alzheimer'S disease using a triaxial accelerometer.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

CA-ABAC: Class Algebra Attribute-Based Access Control.
Proceedings of the 2012 IEEE/WIC/ACM International Conferences on Web Intelligence and Intelligent Agent Technology, 2012

A probabilistic analysis method for functional qualification under Mutation Analysis.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
A register-transfer level testability analyzer.
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

On rewiring and simplification for canonicity in threshold logic circuits.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Automated mapping for reconfigurable single-electron transistor arrays.
Proceedings of the 48th Design Automation Conference, 2011

2010
Fast Node Merging With Don't Cares Using Logic Implications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

The Cadabia Cloud.
Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2010

Distributed Transactions for Semantic Web Workflows - Overcoming the CAP Limitations on Virtual Organizations.
Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2010

Node addition and removal in the presence of don't cares.
Proceedings of the 47th Design Automation Conference, 2010

2009
Dependent-Latch Identification in Reachable State Space.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

A novel ACO-based pattern generation for peak power estimation in VLSI circuits.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

An efficient approach to sip design integration.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Fast detection of node mergers using logic implications.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Enhancing SAT-based sequential depth computation by pruning search space.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

Rewiring using IRredundancy Removal and Addition.
Proceedings of the Design, Automation and Test in Europe, 2009

Dependent latch identification in the reachable state space.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
Novel Probabilistic Combinational Equivalence Checking.
IEEE Trans. Very Large Scale Integr. Syst., 2008

An Implicit Approach to Minimizing Range-Equivalent Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Synthesis of reversible sequential elements.
ACM J. Emerg. Technol. Comput. Syst., 2008

Verification of Pin-Accurate Port Connections.
IEEE Des. Test Comput., 2008

A Statistic-Based Approach to Testability Analysis.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

A Ring-Based Decentralized Collaborative Non-blocking Atomic Commit Protocol.
Proceedings of the 2008 IEEE/WIC/ACM International Conference on Intelligent Agent Technology, 2008

2007
A Bus-Encoding Scheme for Crosstalk Elimination in High-Performance Processor Design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Intelligent Random Vector Generator Based on Probability Analysis of Circuit Structure.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Recognition of Fanout-free Functions.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
PEACH: A Novel Architecture for Probabilistic Combinational Equivalence Checking.
Proceedings of the IFIP VLSI-SoC 2006, 2006

Language-Based High Level Transaction Extraction on On-chip Buses.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

The Potential and Limitation of Probability-Based Combinational Equivalence Checking.
Proceedings of the 15th Asian Test Symposium, 2006

High level equivalence symmetric input identification.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
An Improved Approach for AlternativeWires Identi.cation.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

2004
Using a Class Algebra Ontology To Define Conversions between OWL/SQL/Java Beans.
Proceedings of the 2004 IEEE/WIC/ACM International Conference on Web Intelligence (WI 2004), 2004

Verification on Port Connections.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Graph Automorphism-Based Algorithm for Determining Symmetric Inputs.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

2003
Automatic interconnection rectification for SoC design verification based on the port order fault model.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

SoC design integration by using automatic interconnection rectification.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

An automatic interconnection rectification technique for SoC design integration.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
An automorphic approach to verification pattern generation for SoC design verification using port-order fault model.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

On automatic-verification pattern generation for SoC withport-order fault model.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

2001
An AVPG for SOC design verification with port order fault model.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

On generation of the minimum pattern set for data path elements in SoC design verification based on port order fault model.
Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop 2001, 2001

An Improved AVPG Algorithm for SoC Design Verification Using Port Order Fault Model.
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001


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