Ching-Yi Huang

According to our database¹, Ching-Yi Huang authored at least 26 papers between 2011 and 2020.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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PhD thesis

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On csauthors.net:

Bibliography

2020

ICCAD-2020 CAD Contest in X-value Equivalence Checking and Benchmark Suite : Invited Talk.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

2019

2019 CAD Contest: Logic Regression on High Dimensional Boolean Space.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2019

2018

Using range-equivalent circuits for facilitating bounded sequential equivalence checking.

[BibT_eX]

[DOI]

Proceedings of the 2018 International Symposium on VLSI Design, 2018

2017

Dynamic Diagnosis for Defective Reconfigurable Single-Electron Transistor Arrays.

[BibT_eX]

[DOI]

Vijaykrishnan Narayanan

IEEE Trans. Very Large Scale Integr. Syst., 2017

ICCAD-2017 CAD contest in resource-aware patch generation.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

2016

Diagnosis and Synthesis for Defective Reconfigurable Single-Electron Transistor Arrays.

[BibT_eX]

[DOI]

Vijaykrishnan Narayanan

IEEE Trans. Very Large Scale Integr. Syst., 2016

Area-Aware Decomposition for Single-Electron Transistor Arrays.

[BibT_eX]

[DOI]

Vijaykrishnan Narayanan

ACM Trans. Design Autom. Electr. Syst., 2016

Minimization of Number of Neurons in Voronoi Diagram-Based Artificial Neural Networks.

[BibT_eX]

[DOI]

IEEE Trans. Multi Scale Comput. Syst., 2016

An Efficient Interpolation-Based Projected Sum of Product Decomposition via Genetic Algorithm.

[BibT_eX]

[DOI]

J. Multiple Valued Log. Soft Comput., 2016

MajorSat: A SAT solver to majority logic.

[BibT_eX]

[DOI]

Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015

Synthesis for Width Minimization in the Single-Electron Transistor Array.

[BibT_eX]

[DOI]

Vijaykrishnan Narayanan

IEEE Trans. Very Large Scale Integr. Syst., 2015

Correctness Analysis and Power Optimization for Probabilistic Boolean Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Synthesis and verification of cyclic combinational circuits.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE International System-on-Chip Conference, 2015

Using structural relations for checking combinationality of cyclic circuits.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

A defect-aware approach for mapping reconfigurable Single-Electron Transistor arrays.

[BibT_eX]

[DOI]

Vijaykrishnan Narayanan

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014

Width minimization in the Single-Electron Transistor array synthesis.

[BibT_eX]

[DOI]

Vijaykrishnan Narayanan

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Rewiring for threshold logic circuit minimization.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013

Verification of Reconfigurable Binary Decision Diagram-Based Single-Electron Transistor Arrays.

[BibT_eX]

[DOI]

Yung-Chih Chen

Chun-Yao Wang

Ching-Yi Huang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Pattern generation for Mutation Analysis using Genetic Algorithms.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Sensitization criterion for threshold logic circuits and its application.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

On reconfigurable single-electron transistor arrays synthesis using reordering techniques.

[BibT_eX]

[DOI]

Vijaykrishnan Narayanan

Proceedings of the Design, Automation and Test in Europe, 2013

2012

Error Injection & Correction: An efficient formal logic restructuring algorithm.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2012

Using "Learning Video Portfolio" to Enhance Students' Metacognition in Authentic Learning.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Conference on Advanced Learning Technologies, 2012

A probabilistic analysis method for functional qualification under Mutation Analysis.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011

A register-transfer level testability analyzer.

[BibT_eX]

[DOI]

Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

On rewiring and simplification for canonicity in threshold logic circuits.

[BibT_eX]

[DOI]

Pin-Yi Kuo

Chun-Yao Wang

Ching-Yi Huang

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Ching-Yi Huang

Timeline

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