Hussain Al-Asaad

According to our database, Hussain Al-Asaad authored at least 31 papers between 1993 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Advancements in Secure Computing: Exploring Automated Repair Debugging and Verification Techniques for Hardware Design.

Alireza Abolhasani Zeraatkar, Parnian Shabani Kamran, Hussain Al-Asaad

Proceedings of the 14th IEEE Annual Computing and Communication Workshop and Conference, 2024

2022

A Brief Survey of Fault Tolerant Techniques for Field Programmable Gate Arrays.

Raihana Yarzada, Divya Singh, Hussain Al-Asaad

Proceedings of the 12th IEEE Annual Computing and Communication Workshop and Conference, 2022

2010

Efficient techniques for reducing error latency in on-line periodic built-in self-test.

Hussain Al-Asaad

IEEE Instrum. Meas. Mag., 2010

A Comparison of NMOS to PMOS Starved Buffer Implementations for the Delay Line in a PWM DC-DC Converters.

Calvin Chiem, Hussain Al-Asaad

Proceedings of the 2010 International Conference on Computer Design, 2010

Time-Redundant Logic-Level Protection Mechanisms from Soft Errors in Digital Systems.

Hussain Al-Asaad

Proceedings of the 2010 International Conference on Computer Design, 2010

2009

Low Power Methodologies and Challenges for PWM DC-DC Converters.

Calvin Chiem, Hussain Al-Asaad

Proceedings of the 2009 International Conference on Computer Design, 2009

Detection and Isolation of Faulty Processors in Multiprocessor Systems via TMR-Based Time Redundant Task Scheduling.

Hussain Al-Asaad

Proceedings of the 2009 International Conference on Computer Design, 2009

2008

A Novel Mutation-Based Validation Paradigm for High-Level Hardware Descriptions.

Jorge Campos, Hussain Al-Asaad

IEEE Trans. Very Large Scale Integr. Syst., 2008

2007

A New Statistical Approach for Glitch Estimation in Combinational Circuits.

Ahmed Sayed, Hussain Al-Asaad

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Efficient Global Fault Collapsing for Combinational Library Modules.

Hussain Al-Asaad

Proceedings of the 2007 International Conference on Computer Design, 2007

2006

Circuit Profiling Mechanisms for High-Level {ATPG}.

Jorge Campos, Hussain Al-Asaad

Proceedings of the Seventh International Workshop on Microprocessor Test and Verification (MTV 2006), 2006

Survey and Evaluation of Low-Power Flip-Flops.

Ahmed Sayed, Hussain Al-Asaad

Proceedings of the 2006 International Conference on Computer Design & Conference on Computing in Nanotechnology, 2006

2005

Search-Space Optimizations for High-Level ATPG.

Jorge Campos, Hussain Al-Asaad

Proceedings of the Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), 2005

EGFC: An exact global fault collapsing tool for combinational circuits.

Hussain Al-Asaad

Proceedings of the Third IASTED International Conference on Circuits, 2005

MVP: a mutation-based validation paradigm.

Jorge Campos, Hussain Al-Asaad

Proceedings of the Tenth IEEE International High-Level Design Validation and Test Workshop 2005, Napa Valley, CA, USA, November 30, 2005

On Increasing the Observability of Modern Microprocessors.

Hector Arteaga, Hussain Al-Asaad

Proceedings of the 2005 International Conference on Computer Design, 2005

A Novel Functional Testing and Verification Technique for Logic Circuits.

Hussain Al-Asaad, Ganesh Valliappan, Lourdes Ramirez

Proceedings of the 2005 International Conference on Computer Design, 2005

2004

Mutation-based validation of high-level microprocessor implementations.

Jorge Campos, Hussain Al-Asaad

Proceedings of the Ninth IEEE International High-Level Design Validation and Test Workshop 2004, 2004

Survey and Evaluation of Low-Power Full-Adder Cells.

Ahmed Sayed, Hussain Al-Asaad

Proceedings of the International Conference on Embedded Systems and Applications, 2004

Approaches for Monitoring Vectors on Microprocessor Buses.

Hector Arteaga, Hussain Al-Asaad

Proceedings of the International Conference on Embedded Systems and Applications, 2004

2003

Fault Tolerance for Multiprocessor Systems Via Time Redundant Task Scheduling.

Hussain Al-Asaad, Alireza Sarvi

Proceedings of the International Conference on VLSI, 2003

2000

Logic Design Validation via Simulation and Automatic Test Pattern Generation.

Hussain Al-Asaad, John P. Hayes

J. Electron. Test., 2000

ESIM: A Multimodel Design Error and Fault Simulator for Logic Circuits.

Hussain Al-Asaad, John P. Hayes

Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

1998

Lifetime validation of digital systems via fault modeling and test generation.

Hussain Al-Asaad

PhD thesis, 1998

High-level design verification of microprocessors via error modeling.

David Van Campenhout, Hussain Al-Asaad, John P. Hayes, Trevor N. Mudge, Richard B. Brown

ACM Trans. Design Autom. Electr. Syst., 1998

Scalable Test Generators for High-Speed Datapath Circuits.

Hussain Al-Asaad, John P. Hayes, Brian T. Murray

J. Electron. Test., 1998

Online BIST for Embedded Systems.

Hussain Al-Asaad, Brian T. Murray, John P. Hayes

IEEE Des. Test Comput., 1998

1995

Design verification via simulation and automatic test pattern generation.

Hussain Al-Asaad, John P. Hayes

Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

1994

Distributed Reconfiguration of Fault Tolerant VLSI Mulipipeline Arrays with Constant Interstage Path Lengths.

Hussain Al-Asaad, Mankuan Michael Vai, James Feldman

Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

1993

Concurrent error correction in iterative circuits by recomputing with partitioning and voting.

Hussain Al-Asaad, Edward C. Czeck

Proceedings of the 11th IEEE VLSI Test Symposium (VTS'93), 1993

A Two-Phase Reconfiguration Strategy for Extracting Linear Arrays Out of Two-Dimensional Architectures.

Hussain Al-Asaad, Elias S. Manolakos

Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1993