Brian T. Murray

IEEE Trans. Parallel Distributed Syst., 2005

Dependable communication synthesis for distributed embedded systems.

[BibT_eX]

[DOI]

Rajesh Venkatasubramanian

Reliab. Eng. Syst. Saf., 2005

2003

Low-Cost On-Line Fault Detection Using Control Flow Assertions.

[BibT_eX]

[DOI]

Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003

2002

Time-Constrained Failure Diagnosis in Distributed Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the 2002 International Conference on Dependable Systems and Networks (DSN 2002), 2002

2000

Deterministic built-in test pattern generation for high-performance circuits using twisted-ring counters.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2000

Providing convincing evidence of safety in X-by-wire automotive systems.

[BibT_eX]

[DOI]

Barbara J. Czerny

Joseph G. D'Ambrosio

Proceedings of the 5th IEEE International Symposium on High-Assurance Systems Engineering (HASE 2000), 2000

1999

Deterministic Built-in Pattern Generation for Sequential Circuits.

[BibT_eX]

[DOI]

J. Electron. Test., 1999

Built-in Test Pattern Generation For High-Performance Cir cuits Using Twisted-Ring Counters.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

Tolerating Transient Faults in Statically Scheduled Safety-Critical Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the Eighteenth Symposium on Reliable Distributed Systems, 1999

1998

Huffman encoding of test sets for sequential circuits.

[BibT_eX]

[DOI]

IEEE Trans. Instrum. Meas., 1998

Design of built-in test generator circuits using width compression.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

Optimal Zero-Aliasing Space Compaction of Test Responses.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1998

Scalable Test Generators for High-Speed Datapath Circuits.

[BibT_eX]

[DOI]

Hussain Al-Asaad

J. Electron. Test., 1998

Online BIST for Embedded Systems.

[BibT_eX]

[DOI]

Hussain Al-Asaad

IEEE Des. Test Comput., 1998

Built-In Self Testing of Sequential Circuits Using Precomputed Test Sets.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

1997

Test Width Compression for Built-In Self Testing.

[BibT_eX]

[DOI]

Jian Liu

Minyao Zhu

Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

1996

Testing ICs: Getting to the Core of the Problem.

[BibT_eX]

[DOI]

Computer, 1996

1995

Optimal Space Compaction of Test Responses.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

1994

Hierarchical testing using precomputed tests for modules.

[BibT_eX]

[DOI]

PhD thesis, 1994

Codesign of architectures for automotive powertrain modules.

[BibT_eX]

[DOI]

IEEE Micro, 1994

1991

Test Propagation Through Modules and Circuits.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

1990

Hierarchical test generation using precomputed tests for modules.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

1989

High-Level Test Generation for VLSI.

[BibT_eX]

[DOI]

Debashis Bhattacharya