Hyein Lee

According to our database, Hyein Lee authored at least 16 papers between 2013 and 2020.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2020

Heuristic Methods for Fine-Grain Exploitation of FDSOI.

Hamed Fatemi, Andrew B. Kahng, Hyein Lee, José Pineda de Gyvez

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

2019

Enhancing sensitivity-based power reduction for an industry IC design context.

Hamed Fatemi, Andrew B. Kahng, Hyein Lee, Jiajia Li, José Pineda de Gyvez

Integr., 2019

2018

PROBE: A Placement, Routing, Back-End-of-Line Measurement Utility.

Alex Kahng, Andrew B. Kahng, Hyein Lee, Jiajia Li

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

2017

MILP-Based Optimization of 2-D Block Masks for Timing-Aware Dummy Segment Removal in Self-Aligned Multiple Patterning Layouts.

Peter Debacker, Kwangsoo Han, Andrew B. Kahng, Hyein Lee, Praveen Raghavan, Lutong Wang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Performance- and energy-aware optimization of BEOL interconnect stack geometry in advanced technology nodes.

Kwangsoo Han, Andrew B. Kahng, Hyein Lee, Lutong Wang

Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

Optimal multi-row detailed placement for yield and model-hardware correlation improvements in sub-10nm VLSI.

Changho Han, Kwangsoo Han, Andrew B. Kahng, Hyein Lee, Lutong Wang, Bangqi Xu

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Vertical M1 Routing-Aware Detailed Placement for Congestion and Wirelength Reduction in Sub-10nm Nodes.

Peter Debacker, Kwangsoo Han, Andrew B. Kahng, Hyein Lee, Praveen Raghavan, Lutong Wang

Proceedings of the 54th Annual Design Automation Conference, 2017

2016

Measuring progress and value of IC implementation technology.

Andrew B. Kahng, Hyein Lee, Jiajia Li

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

2015

Scalable Detailed Placement Legalization for Complex Sub-14nm Constraints.

Kwangsoo Han, Andrew B. Kahng, Hyein Lee

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Evaluation of BEOL design rule impacts using an optimal ILP-based detailed router.

Kwangsoo Han, Andrew B. Kahng, Hyein Lee

Proceedings of the 52nd Annual Design Automation Conference, 2015

2014

Timing margin recovery with flexible flip-flop timing model.

Andrew B. Kahng, Hyein Lee

Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Horizontal benchmark extension for improved assessment of physical CAD research.

Andrew B. Kahng, Hyein Lee, Jiajia Li

Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

Minimum implant area-aware gate sizing and placement.

Andrew B. Kahng, Hyein Lee

Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

2013

Learning-based approximation of interconnect delay and slew in signoff timing tools.

Andrew B. Kahng, Seokhyeong Kang, Hyein Lee, Siddhartha Nath, Jyoti Wadhwani

Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction, 2013

High-performance gate sizing with a signoff timer.

Andrew B. Kahng, Seokhyeong Kang, Hyein Lee, Igor L. Markov, Pankit Thapar

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Smart non-default routing for clock power reduction.

Andrew B. Kahng, Seokhyeong Kang, Hyein Lee

Proceedings of the 50th Annual Design Automation Conference 2013, 2013