Hyunchul Park

According to our database, Hyunchul Park authored at least 14 papers between 2004 and 2012.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2012

Libra: Tailoring SIMD Execution Using Heterogeneous Hardware and Dynamic Configurability.

Yongjun Park, Jason Jong Kyu Park, Hyunchul Park, Scott A. Mahlke

Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012

SIMD defragmenter: efficient ILP realization on data-parallel architectures.

Yongjun Park, Sangwon Seo, Hyunchul Park, Hyoun Kyu Cho, Scott A. Mahlke

Proceedings of the 17th International Conference on Architectural Support for Programming Languages and Operating Systems, 2012

2010

Resource recycling: putting idle resources to work on a composable accelerator.

Yongjun Park, Hyunchul Park, Scott A. Mahlke, Sukjin Kim

Proceedings of the 2010 International Conference on Compilers, 2010

2009

Polymorphic Pipeline Array: A Flexible Multicore Accelerator for Mobile Multimedia Applications.

Hyunchul Park

PhD thesis, 2009

A dataflow-centric approach to design low power control paths in CGRAs.

Hyunchul Park, Yongjun Park, Scott A. Mahlke

Proceedings of the IEEE 7th Symposium on Application Specific Processors, 2009

Polymorphic pipeline array: a flexible multicore accelerator with virtualized execution for mobile multimedia applications.

Hyunchul Park, Yongjun Park, Scott A. Mahlke

Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009

Recurrence cycle aware modulo scheduling for coarse-grained reconfigurable architectures.

Taewook Oh, Bernhard Egger, Hyunchul Park, Scott A. Mahlke

Proceedings of the 2009 ACM SIGPLAN/SIGBED conference on Languages, 2009

CGRA express: accelerating execution using dynamic operation fusion.

Yongjun Park, Hyunchul Park, Scott A. Mahlke

Proceedings of the 2009 International Conference on Compilers, 2009

2008

Modulo scheduling for highly customized datapaths to increase hardware reusability.

Kevin Fan, Hyunchul Park, Manjunath Kudlur, Scott A. Mahlke

Proceedings of the Sixth International Symposium on Code Generation and Optimization (CGO 2008), 2008

Edge-centric modulo scheduling for coarse-grained reconfigurable architectures.

Hyunchul Park, Kevin Fan, Scott A. Mahlke, Taewook Oh, Heeseok Kim, Hong-Seok Kim

Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques, 2008

2006

Increasing hardware efficiency with multifunction loop accelerators.

Kevin Fan, Manjunath Kudlur, Hyunchul Park, Scott A. Mahlke

Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

Modulo graph embedding: mapping applications onto coarse-grained reconfigurable architectures.

Hyunchul Park, Kevin Fan, Manjunath Kudlur, Scott A. Mahlke

Proceedings of the 2006 International Conference on Compilers, 2006

2005

Cost Sensitive Modulo Scheduling in a Loop Accelerator Synthesis System.

Kevin Fan, Manjunath Kudlur, Hyunchul Park, Scott A. Mahlke

Proceedings of the 38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-38 2005), 2005

2004

Application-Specific Processing on a General-Purpose Core via Transparent Instruction Set Customization.

Nathan Clark, Manjunath Kudlur, Hyunchul Park, Scott A. Mahlke, Krisztián Flautner

Proceedings of the 37th Annual International Symposium on Microarchitecture (MICRO-37 2004), 2004