I. Lu

According to our database, I. Lu authored at least 2 papers between 2024 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2025

Crossed Bit Line (CBL) Architecture in 3D Flash Memory CMOS Directly Bonded to Array (CBA) Structure.

Hiroshi Maejima, Katsuaki Isobe, N. Okada, Masaki Unno, T. Hashimoto, Tetsuaki Utsumi, T. Hisada, K. Maruyama, Toshiyuki Kouchi, T. Kotani, Hitoshi Shiga, O. Kwon, A. Ganguly, Y. Wu, Hiroki Yabe, I. Lu, F. Toyama, Naohito Morozumi, Masahito Takehara, Takuya Ariki, I. Yoon

Proceedings of the IEEE International Memory Workshop, 2025

2024

Energy Efficiency Scaling for 2 Decades (EES2) Roadmap for Computing.

T. Kaarsberg, J. Atulasimha, J. Baniecki, P. Fischer, S. Pawlowski, S. Misra, A. Bhavnagarwala, E. Salman, M. Ahmed, N. Li, R. Aggarwal, B. Hirano, T. Shah, C. Green, J. Booth, P. Sharps, T. McDonald, J. Ballard, Y. Chen, P. Nagapurkar, W. Huang, Dhireesha Kudithipudi, A. Paramonov, F. Musso, A. K. Ziabari, J. Luo, A. K. Petford-Long, D. Gopman, C. Gotama, T. Wei, S. Shaheen, Y. Zhang, I. Lu, K. Shimizu, E. Taylor, N. Johnson, R. Jones, S. Shankar

Proceedings of the IEEE High Performance Extreme Computing Conference, 2024