# Dhireesha Kudithipudi

According to our database

Collaborative distances:

^{1}, Dhireesha Kudithipudi authored at least 92 papers between 2002 and 2021.Collaborative distances:

## Timeline

#### Legend:

Book In proceedings Article PhD thesis Other## Links

#### On csauthors.net:

## Bibliography

2021

TENT: Efficient Quantization of Neural Networks on the tiny Edge with Tapered FixEd PoiNT.

CoRR, 2021

2020

IEEE Trans. Computers, 2020

CoRR, 2020

Proceedings of the NICE '20: Neuro-inspired Computational Elements Workshop, 2020

Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Adaptive Posit: Parameter aware numerical format for deep learning inference on the edge.

Proceedings of the 2020 IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2020

2019

IEEE Trans. Emerg. Top. Comput. Intell., 2019

IEEE Trans. Emerg. Top. Comput. Intell., 2019

Spiking Reservoir Networks: Brain-inspired recurrent algorithms that use random, fixed synaptic strengths.

IEEE Signal Process. Mag., 2019

ACM J. Emerg. Technol. Comput. Syst., 2019

Analysis of Wide and Deep Echo State Networks for Multiscale Spatiotemporal Time Series Forecasting.

CoRR, 2019

Cheetah: Mixed Low-Precision Hardware & Software Co-Design Framework for DNNs on the Edge.

CoRR, 2019

CoRR, 2019

Performance-Efficiency Trade-off of Low-Precision Numerical Formats in Deep Neural Networks.

CoRR, 2019

Proceedings of the 20th International Symposium on Quality Electronic Design, 2019

Proceedings of the International Joint Conference on Neural Networks, 2019

Proceedings of the International Joint Conference on Neural Networks, 2019

Proceedings of the 2019 IEEE Global Conference on Signal and Information Processing, 2019

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018

Nano Commun. Networks, 2018

Semi-Trained Memristive Crossbar Computing Engine with <i>In Situ</i> Learning Accelerator.

ACM J. Emerg. Technol. Comput. Syst., 2018

Semi-Trained Memristive Crossbar Computing Engine with In-Situ Learning Accelerator.

CoRR, 2018

CoRR, 2018

CoRR, 2018

CoRR, 2018

Secure Neural Circuits to Mitigate Correlation Power Analysis on SHA-3 Hash Function.

Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Proceedings of ELM 2018, 2018

2017

IEEE Trans. Neural Networks Learn. Syst., 2017

HTM Spatial Pooler With Memristor Crossbar Circuits for Sparse Biometric Recognition.

IEEE Trans. Biomed. Circuits Syst., 2017

ACM J. Emerg. Technol. Comput. Syst., 2017

Reservoir Computing in Embedded Systems: Three variants of the reservoir algorithm.

IEEE Consumer Electron. Mag., 2017

Proceedings of the 4th ACM International Conference on Nanoscale Computing and Communication, 2017

Invited paper: Resource sharing in feed forward neural networks for energy efficiency.

Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

On-device STDP and synaptic normalization for neuromemristive spiking neural network.

Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Ziksa: On-chip learning accelerator with memristor crossbars for multilevel neural networks.

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Proceedings of the 2017 International Joint Conference on Neural Networks, 2017

Proceedings of the 2017 International Joint Conference on Neural Networks, 2017

A penalized maximum likelihood approach to the adaptive learning of the spatial pooler permanence.

Proceedings of the 2017 International Joint Conference on Neural Networks, 2017

Proceedings of the IEEE International Conference on Rebooting Computing, 2017

2016

Frontiers Robotics AI, 2016

CoRR, 2016

A Mathematical Formalization of Hierarchical Temporal Memory Cortical Learning Algorithm's Spatial Pooler.

CoRR, 2016

CoRR, 2016

Computer, 2016

Proceedings of the 3rd ACM International Conference on Nanoscale Computing and Communication, 2016

Invited: Towards a scalable neuromorphic hardware for classification and prediction with stochastic No-Prop algorithms.

Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

A design of HTM spatial pooler for face recognition using memristor-CMOS hybrid circuits.

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Proceedings of the IEEE International Conference on Rebooting Computing, 2016

2015

Proceedings of the 28th International Conference on VLSI Design, 2015

Reconfigurable hardware architecture of the spatial pooler for hierarchical temporal memory.

Proceedings of the 28th IEEE International System-on-Chip Conference, 2015

Memristive computational architecture of an echo state network for real-time speech-emotion recognition.

Proceedings of the 2015 IEEE Symposium on Computational Intelligence for Security and Defense Applications, 2015

Design and analysis of neuromemristive echo state networks with limited-precision synapses.

Proceedings of the 2015 IEEE Symposium on Computational Intelligence for Security and Defense Applications, 2015

2014

Proceedings of the Network Science and Cybersecurity, 2014

Proceedings of the Network Science and Cybersecurity, 2014

IEEE Trans. Very Large Scale Integr. Syst., 2014

Proceedings of the 27th IEEE International System-on-Chip Conference, 2014

Proceedings of the 27th IEEE International System-on-Chip Conference, 2014

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

A current-mode CMOS/memristor hybrid implementation of an extreme learning machine.

Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

Proceedings of the 5th Annual International Conference on Biologically Inspired Cognitive Architectures, 2014

2013

Proceedings of the Evolutionary Based Solutions for Green Computing, 2013

IEEE Trans. Computers, 2013

Proceedings of the 2013 International Joint Conference on Neural Networks, 2013

2012

Proceedings of the Handbook of Energy-Aware and Green Computing - Two Volume Set., 2012

Proceedings of the 25th International Conference on VLSI Design, 2012

Lightweight energy prediction framework for solar-powered wireless sensor networks.

Proceedings of the IEEE 25th International SOC Conference, 2012

Reconfigurable RRAM for LUT logic mapping: A case study for reliability enhancement.

Proceedings of the IEEE 25th International SOC Conference, 2012

RRAM-based adaptive neural logic block for implementing non-linearly separable functions in a single layer.

Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Proceedings of the 2012 International Green Computing Conference, 2012

Design-time performance evaluation of thermal management policies for SRAM and RRAM based 3D MPSoCs.

Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

2011

J. Low Power Electron., 2011

Execution characteristics of embedded applications on a Pentium 4-based personal computer.

J. Embed. Comput., 2011

Proceedings of the 2011 International Joint Conference on Neural Networks, 2011

Proceedings of the 2011 International Green Computing Conference and Workshops, 2011

2010

Characterization of Variation Aware Nanoscale Static Random Access Memory Designs.

J. Low Power Electron., 2010

Towards integrated circuit thermal profiling for reduced power consumption: Evaluation of distributed sensing techniques.

Proceedings of the International Green Computing Conference 2010, 2010

Ultra low energy standard cell design optimization for performance and placement algorithm.

Proceedings of the International Green Computing Conference 2010, 2010

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Performance enhancement of subthreshold circuits using substrate biasing and charge-boosting buffers.

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

2009

Int. J. Embed. Syst., 2009

Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

2008

IEEE Trans. Multim., 2008

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

2007

J. Low Power Electron., 2007

2006

Performance Analysis of Embedded Applications on a Pentium-4 Based Machine.

Proceedings of the 2006 International Conference on Embedded Systems & Applications, 2006

2005

Implementation of Low Power Digital Multipliers using 10 -Transistor Adder Blocks.

J. Low Power Electron., 2005

Parametrical characterization of leakage power in embedded system caches using gated-VSS.

Proceedings of the Third IASTED International Conference on Circuits, 2005

2004

Impact of nanotechnology on the performance of CMOS digital multipliers.

Proceedings of the Second IASTED International Conference on Circuits, 2004

2002

Proceedings of the Third International Workshop on Digital and Computational Video, 2002