Dhireesha Kudithipudi

According to our database1, Dhireesha Kudithipudi authored at least 92 papers between 2002 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Article 
PhD thesis 
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Links

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Bibliography

2021
TENT: Efficient Quantization of Neural Networks on the tiny Edge with Tapered FixEd PoiNT.
CoRR, 2021

2020
Neuromorphic System for Spatial and Temporal Information Processing.
IEEE Trans. Computers, 2020

End-to-End Memristive HTM System for Pattern Recognition and Sequence Prediction.
CoRR, 2020

Relational Neurogenesis for Lifelong Learning Agents.
Proceedings of the NICE '20: Neuro-inspired Computational Elements Workshop, 2020

FeFET-Based Neuromorphic Architecture with On-Device Feedback Alignment Training.
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

Metaplasticity in Multistate Memristor Synaptic Networks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Adaptive Posit: Parameter aware numerical format for deep learning inference on the edge.
Proceedings of the 2020 IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2020

2019
Neuromorphic Architecture for the Hierarchical Temporal Memory.
IEEE Trans. Emerg. Top. Comput. Intell., 2019

Guest Editorial: Special Issue on New Trends in Smart Chips and Smart Hardware.
IEEE Trans. Emerg. Top. Comput. Intell., 2019

Spiking Reservoir Networks: Brain-inspired recurrent algorithms that use random, fixed synaptic strengths.
IEEE Signal Process. Mag., 2019

Neuromemrisitive Architecture of HTM with On-Device Learning and Neurogenesis.
ACM J. Emerg. Technol. Comput. Syst., 2019

Analysis of Wide and Deep Echo State Networks for Multiscale Spatiotemporal Time Series Forecasting.
CoRR, 2019

Cheetah: Mixed Low-Precision Hardware & Software Co-Design Framework for DNNs on the Edge.
CoRR, 2019

Deep Learning Training on the Edge with Low-Precision Posits.
CoRR, 2019

Performance-Efficiency Trade-off of Low-Precision Numerical Formats in Deep Neural Networks.
CoRR, 2019

Task-Based Neuromodulation Architecture for Lifelong Learning.
Proceedings of the 20th International Symposium on Quality Electronic Design, 2019

Neuromemristive Multi-Layer Random Projection Network with On-Device Learning.
Proceedings of the International Joint Conference on Neural Networks, 2019

Exploiting Randomness in Deep Learning Algorithms.
Proceedings of the International Joint Conference on Neural Networks, 2019

Stochastic Tucker-Decomposed Recurrent Neural Networks for Forecasting.
Proceedings of the 2019 IEEE Global Conference on Signal and Information Processing, 2019

Deep Positron: A Deep Neural Network Using the Posit Number System.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
Neuromorphic and cognitive computing and communication in hardware.
Nano Commun. Networks, 2018

Semi-Trained Memristive Crossbar Computing Engine with <i>In Situ</i> Learning Accelerator.
ACM J. Emerg. Technol. Comput. Syst., 2018

Semi-Trained Memristive Crossbar Computing Engine with In-Situ Learning Accelerator.
CoRR, 2018

Mod-DeepESN: Modular Deep Echo State Network.
CoRR, 2018

Deep Learning Inference on Embedded Devices: Fixed-Point vs Posit.
CoRR, 2018

On the Statistical Challenges of Echo State Networks and Some Potential Remedies.
CoRR, 2018

Secure Neural Circuits to Mitigate Correlation Power Analysis on SHA-3 Hash Function.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

On-Device Learning in Memristor Spiking Neural Networks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Scalable IP Core for Feed Forward Random Networks.
Proceedings of ELM 2018, 2018

2017
Editorial: A Successful Year and Looking Forward to 2017 and Beyond.
IEEE Trans. Neural Networks Learn. Syst., 2017

HTM Spatial Pooler With Memristor Crossbar Circuits for Sparse Biometric Recognition.
IEEE Trans. Biomed. Circuits Syst., 2017

Stochastic CBRAM-Based Neuromorphic Time Series Prediction System.
ACM J. Emerg. Technol. Comput. Syst., 2017

Reservoir Computing in Embedded Systems: Three variants of the reservoir algorithm.
IEEE Consumer Electron. Mag., 2017

On accelerating stochastic neural networks.
Proceedings of the 4th ACM International Conference on Nanoscale Computing and Communication, 2017

Invited paper: Resource sharing in feed forward neural networks for energy efficiency.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

On-device STDP and synaptic normalization for neuromemristive spiking neural network.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Ziksa: On-chip learning accelerator with memristor crossbars for multilevel neural networks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Extreme learning machine as a generalizable classification engine.
Proceedings of the 2017 International Joint Conference on Neural Networks, 2017

Robustness of a memristor based liquid state machine.
Proceedings of the 2017 International Joint Conference on Neural Networks, 2017

A penalized maximum likelihood approach to the adaptive learning of the spatial pooler permanence.
Proceedings of the 2017 International Joint Conference on Neural Networks, 2017

Convolutional Drift Networks for Video Classification.
Proceedings of the IEEE International Conference on Rebooting Computing, 2017

2016
A Mathematical Formalization of Hierarchical Temporal Memory's Spatial Pooler.
Frontiers Robotics AI, 2016

Non-volatile Hierarchical Temporal Memory: Hardware for Spatial Pooling.
CoRR, 2016

A Mathematical Formalization of Hierarchical Temporal Memory Cortical Learning Algorithm's Spatial Pooler.
CoRR, 2016

Unsupervised Learning in Neuromemristive Systems.
CoRR, 2016

Neuromemristive Systems: Boosting Efficiency through Brain-Inspired Computing.
Computer, 2016

Reconfigurable Digital Design of a Liquid State Machine for Spatio-Temporal Data.
Proceedings of the 3rd ACM International Conference on Nanoscale Computing and Communication, 2016

Invited: Towards a scalable neuromorphic hardware for classification and prediction with stochastic No-Prop algorithms.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

A design of HTM spatial pooler for face recognition using memristor-CMOS hybrid circuits.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Digital neuromorphic design of a Liquid State Machine for real-time processing.
Proceedings of the IEEE International Conference on Rebooting Computing, 2016

2015
Comparison of Off-Chip Training Methods for Neuromemristive Systems.
Proceedings of the 28th International Conference on VLSI Design, 2015

Reconfigurable hardware architecture of the spatial pooler for hierarchical temporal memory.
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015

Memristive computational architecture of an echo state network for real-time speech-emotion recognition.
Proceedings of the 2015 IEEE Symposium on Computational Intelligence for Security and Defense Applications, 2015

Design and analysis of neuromemristive echo state networks with limited-precision synapses.
Proceedings of the 2015 IEEE Symposium on Computational Intelligence for Security and Defense Applications, 2015

2014
Nanoelectronics and Hardware Security.
Proceedings of the Network Science and Cybersecurity, 2014

Design of Neuromorphic Architectures with Memristors.
Proceedings of the Network Science and Cybersecurity, 2014

Temperature Sensing RRAM Architecture for 3-D ICs.
IEEE Trans. Very Large Scale Integr. Syst., 2014

A stochastic learning algorithm for neuromemristive systems.
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014

On designing circuit primitives for cortical processors with memristive hardware.
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014

Neuromemristive Extreme Learning Machines for Pattern Classification.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

A current-mode CMOS/memristor hybrid implementation of an extreme learning machine.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

Memristive Reservoir Computing Architecture for Epileptic Seizure Detection.
Proceedings of the 5th Annual International Conference on Biologically Inspired Cognitive Architectures, 2014

2013
Thermal Management in Many Core Systems.
Proceedings of the Evolutionary Based Solutions for Green Computing, 2013

Memristor-Based Neural Logic Blocks for Nonlinearly Separable Functions.
IEEE Trans. Computers, 2013

Periodic activation functions in memristor-based analog neural networks.
Proceedings of the 2013 International Joint Conference on Neural Networks, 2013

2012
Subthreshold Computing.
Proceedings of the Handbook of Energy-Aware and Green Computing - Two Volume Set., 2012

Towards Thermal Profiling in CMOS/Memristor Hybrid RRAM Architectures.
Proceedings of the 25th International Conference on VLSI Design, 2012

Lightweight energy prediction framework for solar-powered wireless sensor networks.
Proceedings of the IEEE 25th International SOC Conference, 2012

Reconfigurable RRAM for LUT logic mapping: A case study for reliability enhancement.
Proceedings of the IEEE 25th International SOC Conference, 2012

RRAM-based adaptive neural logic block for implementing non-linearly separable functions in a single layer.
Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012

RRAM Motifs for Mitigating Differential Power Analysis Attacks (DPA).
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Temperature-aware computing: Achievements and remaining challenges.
Proceedings of the 2012 International Green Computing Conference, 2012

Design-time performance evaluation of thermal management policies for SRAM and RRAM based 3D MPSoCs.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

2011
Hybrid Subthreshold and Nearthreshold Design Methodology for Energy Minimization.
J. Low Power Electron., 2011

Execution characteristics of embedded applications on a Pentium 4-based personal computer.
J. Embed. Comput., 2011

Reconfigurable N-level memristor memory design.
Proceedings of the 2011 International Joint Conference on Neural Networks, 2011

Cooling mechanisms in 3D ICs: Thermo-mechanical perspective.
Proceedings of the 2011 International Green Computing Conference and Workshops, 2011

2010
Characterization of Variation Aware Nanoscale Static Random Access Memory Designs.
J. Low Power Electron., 2010

Towards integrated circuit thermal profiling for reduced power consumption: Evaluation of distributed sensing techniques.
Proceedings of the International Green Computing Conference 2010, 2010

Ultra low energy standard cell design optimization for performance and placement algorithm.
Proceedings of the International Green Computing Conference 2010, 2010

Variation tolerant 9T SRAM cell design.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Performance enhancement of subthreshold circuits using substrate biasing and charge-boosting buffers.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

2009
Implications of gated-Vss technique on leakage power in embedded caches.
Int. J. Embed. Syst., 2009

Topology selection of FPGA look-up tables for low-leakage operation.
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

2008
Caches for Multimedia Workloads: Power and Energy Tradeoffs.
IEEE Trans. Multim., 2008

GALEOR: Leakage reduction for CMOS circuits.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

2007
Static Power Analysis and Estimation in Ternary Content Addressable Memory Cells.
J. Low Power Electron., 2007

2006
Performance Analysis of Embedded Applications on a Pentium-4 Based Machine.
Proceedings of the 2006 International Conference on Embedded Systems & Applications, 2006

2005
Implementation of Low Power Digital Multipliers using 10 -Transistor Adder Blocks.
J. Low Power Electron., 2005

Parametrical characterization of leakage power in embedded system caches using gated-VSS.
Proceedings of the Third IASTED International Conference on Circuits, 2005

2004
Impact of nanotechnology on the performance of CMOS digital multipliers.
Proceedings of the Second IASTED International Conference on Circuits, 2004

2002
Cache performance of video computation workloads.
Proceedings of the Third International Workshop on Digital and Computational Video, 2002


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