I. Thoidis

According to our database1, I. Thoidis authored at least 2 papers between 1998 and 1999.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

1999
The design of low power multiple-valued logic encoder and decoder circuits.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

1998
Multiple-Valued Logic Voltage-Mode Storage Circuits Based On True-Single-Phase Clocked Logic.
Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998


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