Dimitrios Soudris
Orcid: 0000-0002-6930-6847
According to our database1,
Dimitrios Soudris
authored at least 503 papers
between 1991 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
-
on orcid.org
On csauthors.net:
Bibliography
2024
HW/SW co-design on embedded SoC FPGA for star tracking optimization in space applications.
J. Real Time Image Process., February, 2024
2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023
Co-Design of Approximate Multilayer Perceptron for Ultra-Resource Constrained Printed Circuits.
IEEE Trans. Computers, September, 2023
A memory footprint optimization framework for Python applications targeting edge devices.
J. Syst. Archit., September, 2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., June, 2023
Thermal-Comfort Aware Online Co-Scheduling Framework for HVAC, Battery Systems, and Appliances in Smart Buildings.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., May, 2023
Bringing Energy Efficiency Closer to Application Developers: An Extensible Software Analysis Framework.
IEEE Trans. Sustain. Comput., 2023
Accelerating AI and Computer Vision for Satellite Pose Estimation on the Intel Myriad X Embedded SoC.
Microprocess. Microsystems, 2023
ACM Comput. Surv., 2023
On-sensor Printed Machine Learning Classification via Bespoke ADC and Decision Tree Co-Design.
CoRR, 2023
Approximate Computing Survey, Part II: Application-Specific & Architectural Approximation Techniques and Applications.
CoRR, 2023
Approximate Computing Survey, Part I: Terminology and Software & Hardware Approximation Techniques.
CoRR, 2023
A New Co-Optimized Hybrid Model Based on Multi-Objective Optimization for Probabilistic Wind Power Forecasting in a Spatio-Temporal Framework.
IEEE Access, 2023
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2023
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2023
Proceedings of the 20th ACM SIGPLAN International Conference on Managed Programming Languages and Runtimes, 2023
Proceedings of the 12th International Conference on Modern Circuits and Systems Technologies, 2023
The Unexpected Efficiency of Bin Packing Algorithms for Dynamic Storage Allocation in the Wild: An Intellectual Abstract.
Proceedings of the 2023 ACM SIGPLAN International Symposium on Memory Management, 2023
Proceedings of the 32nd IEEE International Symposium on Industrial Electronics, 2023
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2023
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2023
Adrias: Interference-Aware Memory Orchestration for Disaggregated Cloud Infrastructures.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023
Proceedings of the 14th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 12th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, 2023
RoaD-RuNNer: Collaborative DNN partitioning and offloading on heterogeneous edge systems.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
Increasing the Fault Tolerance of COTS FPGAs in Space: SEU Mitigation Techniques on MPSoC.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2023
Darly: Deep Reinforcement Learning for QoS-aware scheduling under resource heterogeneity Optimizing serverless video analytics.
Proceedings of the 16th IEEE International Conference on Cloud Computing, 2023
IRIS: Interference and Resource Aware Predictive Orchestration for ML Inference Serving.
Proceedings of the 16th IEEE International Conference on Cloud Computing, 2023
PRAETORIAN: A Framework for the Protection of Critical Infrastructures from advanced Combined Cyber and Physical Threats.
Proceedings of the 18th International Conference on Availability, Reliability and Security, 2023
2022
EXA2PRO: A Framework for High Development Productivity on Heterogeneous Computing Systems.
IEEE Trans. Parallel Distributed Syst., 2022
IEEE Trans. Parallel Distributed Syst., 2022
IEEE Trans. Parallel Distributed Syst., 2022
IEEE Trans. Computers, 2022
Decision support for GPU acceleration by predicting energy savings and programming effort.
Sustain. Comput. Informatics Syst., 2022
Live demonstration of an SDN-reconfigurable, FPGA-based TxRx for an analog-IFoF/mmWave radio access network in an MNO's infrastructure.
JOCN, 2022
Translating quality-driven code change selection to an instance of multiple-criteria decision making.
Inf. Softw. Technol., 2022
IET Blockchain, 2022
Frontiers Neuroinformatics, 2022
Approximate computing, skeleton programming and run-time scheduling in an algorithm for process design and controllability in distributed and heterogeneous infrastructures.
Comput. Chem. Eng., 2022
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022
Combining Fault Tolerance Techniques and COTS SoC Accelerators for Payload Processing in Space.
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022
Towards Employing FPGA and ASIP Acceleration to Enable Onboard AI/ML in Space Applications.
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022
High Level Synthesis Acceleration of Change Detection in Multi-Temporal High Resolution Sentinel-2 Satellite Images.
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022
The Impact of Dynamic Storage Allocation on CPython Execution Time, Memory Footprint and Energy Consumption: An Empirical Study.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2022
LSTM Acceleration with FPGA and GPU Devices for Edge Computing Applications in B5G MEC.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2022
End-to-End Real-Time Service Provisioning over a SDN-controllable 60 GHz analog FiWi X-haul for 5G Hot-Spot Networks.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2022
Proceedings of the 11th International Conference on Modern Circuits and Systems Technologies, 2022
MAx-DNN: Multi-Level Arithmetic Approximation for Energy-Efficient DNN Hardware Accelerators.
Proceedings of the 13th IEEE Latin America Symposium on Circuits and System, 2022
Improving the performance of RISC-V softcores on FPGA by exploiting PVT variability and DVFS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Energy Consumption Evaluation of Optane DC Persistent Memory for Indexing Data Structures.
Proceedings of the 29th IEEE International Conference on High Performance Computing, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
SDK4ED: One-click platform for Energy-aware, Maintainable and Dependable Applications.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
Memory Management Methodology for Application Data Structure Refinement and Placement on Heterogeneous DRAM/NVM Systems.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
Proceedings of the IEEE International Conference on Omni-layer Intelligent Systems, 2022
Proceedings of the IEEE 15th International Conference on Cloud Computing, 2022
Proceedings of the ARES 2022: The 17th International Conference on Availability, Reliability and Security, Vienna,Austria, August 23, 2022
2021
Benchmark dataset for preprint: "EDEN: A high-performance, general-purpose, NeuroML-based neural simulator".
Dataset, September, 2021
Benchmark dataset for preprint: "EDEN: A high-performance, general-purpose, NeuroML-based neural simulator".
Dataset, September, 2021
Process Variability Analysis in Interconnect, Logic, and Arithmetic Blocks of 16-nm FinFET FPGAs.
ACM Trans. Reconfigurable Technol. Syst., 2021
Rusty: Runtime Interference-Aware Predictive Monitoring for Modern Multi-Tenant Systems.
IEEE Trans. Parallel Distributed Syst., 2021
Improving Power of DSP and CNN Hardware Accelerators Using Approximate Floating-point Multipliers.
ACM Trans. Embed. Comput. Syst., 2021
Improving Performance-Power-Programmability in Space Avionics with Edge Devices: VBN on Myriad2 SoC.
ACM Trans. Embed. Comput. Syst., 2021
Sustain. Comput. Informatics Syst., 2021
A Flexible Tool for Estimating Applications Performance and Energy Consumption Through Static Analysis.
SN Comput. Sci., 2021
Experience With Managing Technical Debt in Scientific Software Development Using the EXA2PRO Framework.
IEEE Access, 2021
Development and Testing on the European Space-Grade BRAVE FPGAs: Evaluation of NG-Large Using High-Performance DSP Benchmarks.
IEEE Access, 2021
FaaS and Curious: Performance Implications of Serverless Functions on Edge Computing Platforms.
Proceedings of the High Performance Computing - ISC High Performance Digital 2021 International Workshops, Frankfurt am Main, Germany, June 24, 2021
FADE: FaaS-inspired application decomposition and Energy-aware function placement on the Edge.
Proceedings of the SCOPES '21: 24th International Workshop on Software and Compilers for Embedded Systems, Eindhoven, The Netherlands, November 1, 2021
Interference-Aware Workload Placement for Improving Latency Distribution of Converged HPC/Big Data Cloud Infrastructures.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2021
The Known Unknowns: Discovering Trade-Offs Between Heterogeneous Code Changes - Invited Paper.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2021
Proceedings of the 10th International Conference on Modern Circuits and Systems Technologies, 2021
Proceedings of the 10th International Conference on Modern Circuits and Systems Technologies, 2021
Towards sharing one FPGA SoC for both low-level PHY and high-level AI/ML computing at the edge.
Proceedings of the IEEE International Mediterranean Conference on Communications and Networking, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
FPGA & VPU Co-Processing in Space Applications: Development and Testing with DSP/AI Benchmarks.
Proceedings of the 28th IEEE International Conference on Electronics, 2021
Proceedings of the 12th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and 10th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, 2021
Proceedings of the HEART '21: 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2021
Exploiting the Potential of Approximate Arithmetic in DSP & AI Hardware Accelerators.
Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021
Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021
Demonstration of FPGA-based A-IFoF/mmWave transceiver integration in mobile infrastructure for beyond 5G transport.
Proceedings of the European Conference on Optical Communication, 2021
Proceedings of the 24th Euromicro Conference on Digital System Design, 2021
Thermal Comfort Aware Online Energy Management Framework for a Smart Residential Building.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
EVOLVE: HPC and cloud enhanced testbed for extracting value from large-scale diverse data.
Proceedings of the CF '21: Computing Frontiers Conference, 2021
Covid4HPC: A Fast and Accurate Solution for Covid Detection in the Cloud Using X-Rays.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2021
2020
High-Performance Vision-Based Navigation on SoC FPGA for Spacecraft Proximity Operations.
IEEE Trans. Circuits Syst. Video Technol., 2020
Rapid Prototyping of Low-Complexity Orchestrator Targeting CyberPhysical Systems: The Smart-Thermostat Usecase.
IEEE Trans. Control. Syst. Technol., 2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Analog fiber-wireless downlink transmission of IFoF/mmWave over in-field deployed legacy PON infrastructure for 5G fronthauling.
JOCN, 2020
CoRR, 2020
Proceedings of the High Performance Computing, 2020
Portable exploitation of parallel and heterogeneous HPC architectures in neural simulation using SkePU.
Proceedings of the SCOPES '20: 23rd International Workshop on Software and Compilers for Embedded Systems, 2020
Proceedings of the SCOPES '20: 23rd International Workshop on Software and Compilers for Embedded Systems, 2020
Technical Debt Management and Energy Consumption Evaluation in Implantable Medical Devices: The SDK4ED Approach.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2020
Proceedings of the 9th International Conference on Modern Circuits and Systems Technologies, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Memory Footprint Optimization Techniques for Machine Learning Applications in Embedded Systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020
The SDK4ED Platform for Embedded Software Quality Improvement - Preliminary Overview.
Proceedings of the Computational Science and Its Applications - ICCSA 2020, 2020
Proceedings of the 28th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
Proceedings of the 17th ACM International Conference on Computing Frontiers, 2020
Proceedings of the 20th IEEE International Conference on Bioinformatics and Bioengineering, 2020
Exploiting the SoC FPGA Capabilities in the Control Architecture of a Quadruped Robot.
Proceedings of the IEEE/ASME International Conference on Advanced Intelligent Mechatronics, 2020
2019
ACM Trans. Internet Techn., 2019
A Closed-Loop Controller to Ensure Performance and Temperature Constraints for Dynamic Applications.
ACM Trans. Embed. Comput. Syst., 2019
ACM Trans. Embed. Comput. Syst., 2019
IEEE Trans. Circuits Syst. II Express Briefs, 2019
A Message-Passing Microcoded Synchronization for Distributed Shared Memory Architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
IEEE Trans. Computers, 2019
Failure probability of a FinFET-based SRAM cell utilizing the most probable failure point.
Integr., 2019
Neurocomputing, 2019
IET Circuits Devices Syst., 2019
IEEE Comput. Archit. Lett., 2019
IEEE Comput. Archit. Lett., 2019
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019
Proceedings of the 14th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2019
A Synergy of a Closed-Loop DVFS Controller and CPU Hot-Plug For Run-Time Thermal Management in Multicore Systems.
Proceedings of the 29th International Symposium on Power and Timing Modeling, 2019
Proceedings of the Optical Network Design and Modeling, 2019
Proceedings of the 8th International Conference on Modern Circuits and Systems Technologies, 2019
TF2FPGA: A Framework for Projecting and Accelerating Tensorflow CNNs on FPGA Platforms.
Proceedings of the 8th International Conference on Modern Circuits and Systems Technologies, 2019
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019
Dataflow Acceleration of Smith-Waterman with Traceback for High Throughput Next Generation Sequencing.
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019
Co-design Implications of Cost-effective On-demand Acceleration for Cloud Healthcare Analytics: The AEGLE approach.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Cooperative Arithmetic-Aware Approximation Techniques for Energy-Efficient Multipliers.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
Proceedings of the International Conference on Omni-Layer Intelligent Systems, 2019
GPU Implementation of Neural-Network Simulations Based on Adaptive-Exponential Models.
Proceedings of the 19th IEEE International Conference on Bioinformatics and Bioengineering, 2019
2018
High-Performance Embedded Computing in Space: Evaluation of Platforms for Vision-Based Navigation.
J. Aerosp. Inf. Syst., April, 2018
VOSsim: A Framework for Enabling Fast Voltage Overscaling Simulation for Approximate Computing Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2018
IEEE Trans. Very Large Scale Integr. Syst., 2018
ACM Trans. Design Autom. Electr. Syst., 2018
Application-Arrival Rate Aware Distributed Run-Time Resource Management for Many-Core Computing Platforms.
IEEE Trans. Multi Scale Comput. Syst., 2018
A Hierarchical Distributed Runtime Resource Management Scheme for NoC-Based Many-Cores.
ACM Trans. Embed. Comput. Syst., 2018
ACM Trans. Embed. Comput. Syst., 2018
ACM Trans. Cyber Phys. Syst., 2018
A Design Space Exploration Framework for Convolutional Neural Networks Implemented on Edge Devices.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
IEEE Micro, 2018
IEEE Comput. Archit. Lett., 2018
CF-TUNE: Collaborative Filtering Auto-Tuning for Energy Efficient Many-Core Processors.
IEEE Comput. Archit. Lett., 2018
Interrelations between Software Quality Metrics, Performance and Energy Consumption in Embedded Applications.
Proceedings of the 21st International Workshop on Software and Compilers for Embedded Systems, 2018
Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018
Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018
BLonD++: performance analysis and optimizations for enabling complex, accurate and fast beam dynamics studies.
Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018
Real-Time Carrier Phase Recovery for 16-QAM Utilizing the Nonlinear Least Squares Algorithm.
Proceedings of the Optical Fiber Communications Conference and Exposition, 2018
Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, 2018
Proceedings of the 7th International Conference on Modern Circuits and Systems Technologies, 2018
Proceedings of the 7th International Conference on Modern Circuits and Systems Technologies, 2018
Carrier Phase Recovery of 64 GBd Optical 16-QAM Using Extensive Parallelization on an FPGA.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
A Novel Framework for the Seamless Integration of FPGA Accelerators with Big Data Analytics Frameworks in Heterogeneous Data Centers.
Proceedings of the 2018 International Conference on High Performance Computing & Simulation, 2018
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018
A Framework Exploiting Process Variability to Improve Energy Efficiency in FPGA Applications.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018
Proceedings of the Workshop on INTelligent Embedded Systems Architectures and Applications, 2018
Proceedings of the 2018 Conference on Design and Architectures for Signal and Image Processing, 2018
Proceedings of the 55th Annual Design Automation Conference, 2018
Efficient Hardware Acceleration of Recommendation Engines: A Use Case on Collaborative Filtering.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018
Seamless FPGA Deployment over Spark in Cloud Computing: A Use Case on Machine Learning Hardware Acceleration.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018
Proceedings of the 2018 NASA/ESA Conference on Adaptive Hardware and Systems, 2018
2017
An Exploration Framework for Efficient High-Level Synthesis of Support Vector Machines: Case Study on ECG Arrhythmia Detection for Xilinx Zynq SoC.
J. Signal Process. Syst., 2017
A Flexible, High-Performance FPGA Implementation of a Feed-Forward Equalizer for Optical Interconnects up to 112 Gb/s.
J. Signal Process. Syst., 2017
J. Signal Process. Syst., 2017
Optimizing Extended Hodgkin-Huxley Neuron Model Simulations for a Xeon/Xeon Phi Node.
IEEE Trans. Parallel Distributed Syst., 2017
SoftRM: Self-Organized Fault-Tolerant Resource Management for Failure Detection and Recovery in NoC Based Many-Cores.
ACM Trans. Embed. Comput. Syst., 2017
On supporting rapid prototyping of embedded systems with reconfigurable architectures.
Integr., 2017
IEEE Embed. Syst. Lett., 2017
From Knights Corner to Landing: A Case Study Based on a Hodgkin-Huxley Neuron Simulator.
Proceedings of the High Performance Computing, 2017
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017
From edge to cloud: Design and implementation of a healthcare Internet of Things infrastructure.
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017
FabSpace 2.0: A platform for application and service development based on Earth Observation data.
Proceedings of the 6th International Conference on Modern Circuits and Systems Technologies, 2017
Proceedings of the 6th International Conference on Modern Circuits and Systems Technologies, 2017
Project HIPNOS: Case Study of High Performance Avionics for Active Debris Removal in Space.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017
AEGLE's Cloud Infrastructure for Resource Monitoring and Containerized Accelerated Analytics.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017
FPGA acceleration of hyperspectral image processing for high-speed detection applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the 2017 IEEE International Geoscience and Remote Sensing Symposium, 2017
Proceedings of the 8th Workshop and 6th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and Design Tools and Architectures for Multicore Embedded Computing Platforms, 2017
Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2017
Energy Efficient Adaptive Approach for Dependable Performance in the presence of Timing Interference.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Application performance improvement by exploiting process variability on FPGA devices.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Proceedings of the Working Notes of CLEF 2017, 2017
Proceedings of the Applied Reconfigurable Computing - 13th International Symposium, 2017
2016
Design-Efficient Approximate Multiplication Circuits Through Partial Product Perforation.
IEEE Trans. Very Large Scale Integr. Syst., 2016
ACM Trans. Embed. Comput. Syst., 2016
An Integrated Exploration and Virtual Platform Framework for Many-Accelerator Heterogeneous Systems.
ACM Trans. Embed. Comput. Syst., 2016
Near-Static Shading Exploration for Smart Photovoltaic Module Topologies Based on Snake-like Configurations.
ACM Trans. Embed. Comput. Syst., 2016
HW/SW Codesign and FPGA Acceleration of Visual Odometry Algorithms for Rover Navigation on Mars.
IEEE Trans. Circuits Syst. Video Technol., 2016
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
A Systematic Methodology for Optimization of Applications Utilizing Concurrent Data Structures.
IEEE Trans. Computers, 2016
Effective Learning and Filtering of Faulty Heart-Beats for Advanced ECG Arrhythmia Detection using MIT-BIH Database.
EAI Endorsed Trans. Pervasive Health Technol., 2016
Customization methodology for implementation of streaming aggregation in embedded systems.
J. Syst. Archit., 2016
Improving Dynamic Memory Allocation on Many-Core Embedded Systems With Distributed Shared Memory.
IEEE Embed. Syst. Lett., 2016
ANT3D: Simultaneous Partitioning and Placement for 3-D FPGAs based on Ant Colony Optimization.
IEEE Embed. Syst. Lett., 2016
CoRR, 2016
IEEE Commun. Surv. Tutorials, 2016
Proceedings of the 3rd IEEE World Forum on Internet of Things, 2016
Performance-power exploration of software-defined big data analytics: The AEGLE cloud backend.
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016
An OpenCL-based framework for rapid virtual prototyping of heterogeneous architectures.
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016
A framework for exploring alternative fault-tolerant schemes targeting 3-D reconfigurable architectures.
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016
Proceedings of the 20th Pan-Hellenic Conference on Informatics, 2016
Energy profile analysis of Zynq-7000 programmable SoC for embedded medical processing: Study on ECG arrhythmia detection.
Proceedings of the 26th International Workshop on Power and Timing Modeling, 2016
Proceedings of the 2016 IEEE International Symposium on Performance Analysis of Systems and Software, 2016
Proceedings of the International Conference on IC Design and Technology, 2016
A 56 Gbaud reconfigurable FPGA feed-forward equalizer for optical datacenter networks with flexible baudrate- and modulation-format.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016
Proceedings of the 7th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and the 5th Workshop on Design Tools and Architectures For Multicore Embedded Computing Platforms, 2016
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016
Approximating Standard Cell Delay Distributions by Reformulating the Most Probable Failure Point.
Proceedings of the Workshop on Early Reliability Modeling for Aging and Variability in Silicon Systems, 2016
Runtime interval optimization and dependable performance for application-level checkpointing.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2016
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016
Proceedings of the 2016 International Conference on Compilers, 2016
The VINEYARD Approach: Versatile, Integrated, Accelerator-Based, Heterogeneous Data Centres.
Proceedings of the Applied Reconfigurable Computing - 12th International Symposium, 2016
2015
Demonstrating HW-SW Transient Error Mitigation on the Single-Chip Cloud Computer Data Plane.
IEEE Trans. Very Large Scale Integr. Syst., 2015
Placement of Linked Dynamic Data Structures over Heterogeneous Memories in Embedded Systems.
ACM Trans. Embed. Comput. Syst., 2015
GENESIS: Parallel Application Placement onto Reconfigurable Architectures (Invited for the Special Issue on Runtime Management).
ACM Trans. Embed. Comput. Syst., 2015
Microprocess. Microsystems, 2015
Using Chaos Theory based workload analysis to perform Dynamic Frequency Scaling on MPSoCs.
J. Syst. Archit., 2015
Performance and power consumption evaluation of concurrent queue implementations in embedded systems.
Comput. Sci. Res. Dev., 2015
IEEE Embed. Syst. Lett., 2015
Classification Framework for Analysis and Modeling of Physically Induced Reliability Violations.
ACM Comput. Surv., 2015
IEEE Comput. Archit. Lett., 2015
IEEE Comput. Archit. Lett., 2015
An Energy Efficient Message Passing Synchronization Algorithm for Concurrent Data Structures in Embedded Systems.
Proceedings of the 18th International Workshop on Software and Compilers for Embedded Systems, 2015
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015
HARPA: Solutions for dependable performance under physically induced performance variability.
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015
Platform-aware dynamic data type refinement methodology for radix tree Data Structures.
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015
Many-core CPUs can deliver scalable performance to stochastic simulations of large-scale biochemical reaction networks.
Proceedings of the 2015 International Conference on High Performance Computing & Simulation, 2015
Efficient Reliability Analysis of Processor Datapath using Atomistic BTI Variability Models.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015
Rapid prototyping and Design Space Exploration methodologies for many-accelerator systems.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015
Job-Arrival Aware Distributed Run-Time Resource Management on Intel SCC Manycore Platform.
Proceedings of the 13th IEEE International Conference on Embedded and Ubiquitous Computing, 2015
Proceedings of the 13th IEEE International Conference on Embedded and Ubiquitous Computing, 2015
SWAN-iCARE Project: On the Efficiency of FPGAs Emulating Wearable Medical Devices for Wound Management and Monitoring.
Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015
Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015
Reconfigurable Computing for Analytics Acceleration of Big Bio-Data: The AEGLE Approach.
Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015
Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015
Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015
Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015
2014
ACM Trans. Embed. Comput. Syst., 2014
ACM Trans. Embed. Comput. Syst., 2014
Microprocess. Microsystems, 2014
J. Syst. Archit., 2014
J. Field Robotics, 2014
Network Function Virtualization based on FPGAs: A Framework for all-Programmable network devices.
CoRR, 2014
Optimal mapping of inferior olive neuron simulations on the Single-Chip Cloud Computer.
Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014
Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014
A HW/SW framework emulating wearable devices for remote wound monitoring and management.
Proceedings of the 4th International Conference on Wireless Mobile Communication and Healthcare: "Transforming healthcare through innovations in mobile and wireless technologies", 2014
SWAN-iCare project: Towards smart wearable and autonomous negative pressure device for wound monitoring and therapy.
Proceedings of the 4th International Conference on Wireless Mobile Communication and Healthcare: "Transforming healthcare through innovations in mobile and wireless technologies", 2014
Hardware accelerated rician denoise algorithm for high performance magnetic resonance imaging.
Proceedings of the 4th International Conference on Wireless Mobile Communication and Healthcare: "Transforming healthcare through innovations in mobile and wireless technologies", 2014
Proceedings of the 2014 International Symposium on System-on-Chip, 2014
Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014
Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014
A Framework for Mapping Dynamic Virtual Kernels onto Heterogeneous Reconfigurable Platforms.
Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014
Understanding timing impact of BTI/RTN with massively threaded atomistic transient simulations.
Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014
Effective Platform-Level Exploration for Heterogeneous Multicores Exploiting Simulation-Induced Slacks.
Proceedings of the 5th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and the 3rd Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, 2014
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014
2013
ACM Trans. Reconfigurable Technol. Syst., 2013
ACM Trans. Embed. Comput. Syst., 2013
System scenarios-based architecture level exploration of SDR application using a network-on-chip simulation framework.
Microprocess. Microsystems, 2013
J. Syst. Archit., 2013
J. Syst. Archit., 2013
Enabling Efficient System Configurations for Dynamic Wireless Applications Using System Scenarios.
Int. J. Wirel. Inf. Networks, 2013
Int. J. Adapt. Resilient Auton. Syst., 2013
SWAN-iCare: A smart wearable and autonomous negative pressure device for wound monitoring and therapy.
Proceedings of the 2013 International Conference on Embedded Computer Systems: Architectures, 2013
Proceedings of the 2013 International Conference on Embedded Computer Systems: Architectures, 2013
Proceedings of the 2013 23rd International Workshop on Power and Timing Modeling, 2013
A new design paradigm for floating point DSP applications based on ESL/HLS and FPGAs?
Proceedings of the IEEE International Symposium on Signal Processing and Information Technology, 2013
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013
A platform-independent runtime methodology for mapping multiple applications onto FPGAs through resource virtualization.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013
Hypervised transient SPICE simulations of large netlists & workloads on multi-processor systems.
Proceedings of the Design, Automation and Test in Europe, 2013
Distributed run-time resource management for malleable applications on many-core platforms.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
2012
A Systematic Methodology for Reliability Improvements on SoC-Based Software Defined Radio Systems.
VLSI Design, 2012
ACM Trans. Reconfigurable Technol. Syst., 2012
Compiler-in-the-loop exploration during datapath synthesis for higher quality delay-area trade-offs.
ACM Trans. Design Autom. Electr. Syst., 2012
Des. Autom. Embed. Syst., 2012
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012
Systematic design and evaluation of a scalable reconfigurable multiplier scheme for HLS environments.
Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2012
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012
Parallel paradigms and run-time management techniques for many-core architectures: the 2PARMA approach.
Proceedings of the 2012 Interconnection Network Architecture, 2012
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012
A divide and conquer based distributed run-time mapping methodology for many-core platforms.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Performance Evaluation of Embedded Processor in MapReduce Cloud Computing Applications.
Proceedings of the Cloud Computing - Third International Conference, 2012
Proceedings of the ARCS 2012 Workshops, 28. Februar - 2. März 2012, München, Germany, 2012
Proceedings of the ARCS 2012 Workshops, 28. Februar - 2. März 2012, München, Germany, 2012
Proceedings of the 2012 NASA/ESA Conference on Adaptive Hardware and Systems, 2012
Proceedings of the 2012 NASA/ESA Conference on Adaptive Hardware and Systems, 2012
2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
Microprocess. Microsystems, 2011
IEEE Embed. Syst. Lett., 2011
Custom Microcoded Dynamic Memory Management for Distributed On-Chip Memory Organizations.
IEEE Embed. Syst. Lett., 2011
Enabling efficient system configurations for dynamic wireless baseband engines using system scenarios.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2011
Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011
SPARTAN project: Efficient implementation of computer vision algorithms onto reconfigurable platform targeting to space applications.
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011
Invited paper: Parallel programming and run-time resource management framework for many-core platforms: The 2PARMA approach.
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
A Heterogeneous Multicore System on Chip with Run-Time Reconfigurable Virtual FPGA Architecture.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011
Power, performance and area prediction of 3D ICs during early stage design exploration in 45nm.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011
A Methodology and Tool Framework for Supporting Rapid Exploration of Memory Hierarchies in FPGAs.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011
A Framework for Architecture-Level Exploration of Communication Intensive Applications onto 3-D FPGAs.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011
Runtime Tuning of Dynamic Memory Management For Mitigating Footprint-Fragmentation Variations.
Proceedings of the ARCS 2011, 2011
Proceedings of the ARCS 2011, 2011
Quick_Hotspot: A Software Supported Methodology for Supporting Run-Time Thermal Analysis at MPSoC Designs.
Proceedings of the ARCS 2011, 2011
2010
Software metadata: Systematic characterization of the memory behaviour of dynamic applications.
J. Syst. Softw., 2010
A Novel Allocation Methodology for Partial and Dynamic Bitstream Generation for FPGA Architectures.
J. Circuits Syst. Comput., 2010
IEEE Embed. Syst. Lett., 2010
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010
Custom multi-threaded Dynamic Memory Management for Multiprocessor System-on-Chip platforms.
Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, 2010
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2010
Efficient High Level Synthesis Exploration Methodology Combining Exhaustive and Gradient-Based Pruned Searching.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010
A High Level Synthesis Exploration Framework with Iterative Design Space Partitioning.
Proceedings of the VLSI 2010 Annual Symposium - Selected papers, 2010
High-Level Synthesis Methodologies for Delay-Area Optimized Coarse-Grained Reconfigurable Coprocessor Architectures.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010
2PARMA: Parallel Paradigms and Run-Time Management Techniques for Many-Core Architectures.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010
2PARMA: Parallel Paradigms and Run-time Management Techniques for Many-Core Architectures.
Proceedings of the VLSI 2010 Annual Symposium - Selected papers, 2010
Systematic Exploration of Energy-Efficient Application-Specific Network-on-Chip Architectures.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010
Proceedings of the VLSI 2010 Annual Symposium - Selected papers, 2010
Proceedings of the VLSI 2010 Annual Symposium - Selected papers, 2010
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010
Designing efficient DSP datapaths through compiler-in-the-loop exploration methodology.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the 17th IEEE International Conference on Electronics, 2010
NAROUTO: An open-source framework for supporting architecture-level exploration at heterogeneous FPGAS.
Proceedings of the 17th IEEE International Conference on Electronics, 2010
Proceedings of the 17th IEEE International Conference on Electronics, 2010
Proceedings of the Design, Automation and Test in Europe, 2010
A framework for automatic parallelization, static and dynamic memory optimization in MPSoC platforms.
Proceedings of the 47th Design Automation Conference, 2010
MNEMEE: a framework for memory management and optimization of static and dynamic data in MPSoCs.
Proceedings of the 2010 International Conference on Compilers, 2010
Proceedings of the ARCS '10, 2010
Proceedings of the ARCS '10, 2010
Proceedings of the Reconfigurable Computing: Architectures, 2010
2009
Optimization methodology of dynamic data structures based on genetic algorithms for multimedia embedded systems.
J. Syst. Softw., 2009
Designing a novel high-performance FPGA architecture for data intensive applications.
J. Real Time Image Process., 2009
Direct memory access usage optimization in network applications for reduced memory latency and energy consumption.
J. Embed. Comput., 2009
J. Embed. Comput., 2009
Int. J. Commun. Syst., 2009
High-level estimation methodology for designing the instruction cache memory of programmable embedded platforms.
IET Comput. Digit. Tech., 2009
Multi-granularity NoC Simulation Framework for Early Phase Exploration of SDR Hardware Platforms.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009
Application-Specific Temperature Reduction Systematic Methodology for 2D and 3D Networks-on-Chip.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009
Three dimensional FPGA architectures: A shift paradigm for energy-performance efficient DSP implementations.
Proceedings of the 16th International Conference on Digital Signal Processing, 2009
Proceedings of the 16th International Conference on Digital Signal Processing, 2009
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009
A software-supported methodology for exploring interconnection architectures targeting 3-D FPGAs.
Proceedings of the Design, Automation and Test in Europe, 2009
2008
A Full-Adder-Based Methodology for the Design of Scaling Operation in Residue Number System.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008
Exploration methodology of dynamic data structures in multimedia and network applications for embedded platforms.
J. Syst. Archit., 2008
Designing a General-Purpose Interconnection Architecture for Field Programmable Gate Arrays.
J. Low Power Electron., 2008
J. Low Power Electron., 2008
Architecture-Level Exploration of Alternative Interconnection Schemes Targeting 3D FPGAs: A Software-Supported Methodology.
Int. J. Reconfigurable Comput., 2008
Proceedings of the VLSI-SoC: Design Methodologies for SoC and SiP, 2008
Proceedings of the VLSI-SoC: Design Methodologies for SoC and SiP, 2008
An Efficient Approach for Managing Power Consumption Hotspots Distribution on 3D FPGAs.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008
Enabling run-time memory data transfer optimizations at the system level with automated extraction of embedded software metadata information.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
Mapping DSP Applications onto High-Performance Architectural Templates with Inlined Flexibility.
Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2008
2007
Automated framework for partitioning DSP applications in hybrid reconfigurable platforms.
Microprocess. Microsystems, 2007
Systematic methodology for exploration of performance - Energy trade-offs in network applications using Dynamic Data Type refinement.
J. Syst. Archit., 2007
Architecture design of a coarse-grain reconfigurable multiply-accumulate unit for data-intensive applications.
Integr., 2007
Systematic methodology for designing low power direct digital frequency synthesisers.
IET Circuits Devices Syst., 2007
Proceedings of the IFIP VLSI-SoC 2007, 2007
A software-supported methodology for designing high-performance 3D FPGA architectures.
Proceedings of the IFIP VLSI-SoC 2007, 2007
Optimization of dynamic data structures in multimedia embedded systems using evolutionary computation.
Proceedings of the 10th International Workshop on Software and Compilers for Embedded Systems, 2007
Systematic Data Structure Exploration of Multimedia and Network Applications realized Embedded Systems.
Proceedings of the 2007 International Conference on Embedded Computer Systems: Architectures, 2007
Direct Memory Access Optimization in Wireless Terminals for Reduced Memory Latency and Energy Consumption.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007
System-Level Application-Specific NoC Design for Network and Multimedia Applications.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007
Design Methodology and Software Tool for Estimation of Multi-level Instruction Cache Memory Miss Rate.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007
Exploring Alternative 3D FPGA Architectures: Design Methodology and CAD Tool Support.
Proceedings of the FPL 2007, 2007
Component Based Library Implementation of Abstract Data Types for Resource Management Customization of Embedded Systems.
Proceedings of the 2007 5th Workshop on Embedded Systems for Real-Time Multimedia, 2007
Middleware design optimization of wireless protocols based on the exploitation of dynamic input patterns.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
Proceedings of the Reconfigurable Computing: Architectures, 2007
Proceedings of the 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), 2007
2006
Behavioral-Level Performance and Power Exploration of Data-Intensive Applications Mapped on Programmable Processors.
J. VLSI Signal Process., 2006
A combined DMA and application-specific prefetching approach for tackling the memory latency bottleneck.
IEEE Trans. Very Large Scale Integr. Syst., 2006
Systematic dynamic memory management design methodology for reduced memory footprint.
ACM Trans. Design Autom. Electr. Syst., 2006
Power Management Through Dynamic Frequency Scaling for Low and Medium Bit-Rate Digital Receivers.
J. Low Power Electron., 2006
Efficient system-level prototyping of power-aware dynamic memory managers for embedded systems.
Integr., 2006
Reducing memory fragmentation in network applications with dynamic memory allocators optimized for performance.
Comput. Commun., 2006
Proceedings of the IFIP VLSI-SoC 2006, 2006
Designing Alternative FPGA Implementations Using Spatial Data from Hardware Resources.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006
A novel methodology for designing high-performance and low-power FPGA interconnection targeting DSP applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Systematic design flow for dynamic data management in visual texture decoder of MPEG-4.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Platform-based FPGA architecture: designing high-performance and low-power routing structure for realizing DSP applications.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006
A novel methodology for designing high-performance and low-energy FPGA routing architecture.
Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, 2006
An Estimation Methodology for Designing Instruction Cache Memory of Embedded Systems.
Proceedings of the 2006 4th Workshop on Embedded Systems for Real-Time Multimedia, 2006
Energy-efficient dynamic memory allocators at the middleware level of embedded systems.
Proceedings of the 6th ACM & IEEE International conference on Embedded software, 2006
Automated exploration of pareto-optimal configurations in parameterized dynamic memory allocation for embedded systems.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Dynamic data type refinement methodology for systematic performance-energy design exploration of network applications.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
2005
Microelectron. J., 2005
A complete platform and toolset for system implementation on fine-grain reconfigurable hardware.
Microprocess. Microsystems, 2005
Memory power optimization of hardware implementations of multimedia applications onto FPGA platforms.
J. Embed. Comput., 2005
J. Circuits Syst. Comput., 2005
A Novel FPGA Architecture and an Integrated Framework of CAD Tools for Implementing Applications.
IEICE Trans. Inf. Syst., 2005
Des. Autom. Embed. Syst., 2005
Reducing Memory Fragmentation with Performance-Optimized Dynamic Memory Allocators in Network Applications.
Proceedings of the Wired/Wireless Internet Communications, Third International Conference, 2005
A Modified Spiral Search Algorithm and its Embedded Hardware Implementation.
Proceedings of the International Enformatika Conference, 2005
Proceedings of the Integrated Circuit and System Design, 2005
A modified spiral search motion estimation algorithm and its embedded system implementation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
DAGGER: A Novel Generic Methodology for FPGA Bitstream Generation and Its Software Tool Implementation.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005
A Framework for Partitioning Computational Intensive Applications in Hybrid Reconfigurable Platforms.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005
An Integrated Framework for Architecture Level Exploration of Reconfigurable Platform.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005
A Memory Hierarchical Layer Assigning and Prefetching Technique to Overcome the Memory Performance/Energy Bottleneck.
Proceedings of the 2005 Design, 2005
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
2004
The low power analogue and digital baseband processing parts of a novel multimode DECT/GSM/DCS1800 terminal.
Microelectron. J., 2004
Design of Energy Efficient Wireless Networks Using Dynamic Data Type Refinement Methodology.
Proceedings of the Wired/Wireless Internet Communications, Second International Conference, 2004
Proceedings of the Computer Systems: Architectures, 2004
Power, Performance and Area Exploration for Data Memory Assignment of Multimedia Applications.
Proceedings of the Computer Systems: Architectures, 2004
Hardware Building Blocks of a Mixed Granularity Reconfigurable System-on-Chip Platform.
Proceedings of the Integrated Circuit and System Design, 2004
Mapping Computational Intensive Applications to a New Coarse-Grained Reconfigurable Data-Path.
Proceedings of the Integrated Circuit and System Design, 2004
Modular Construction and Power Modelling of Dynamic Memory Managers for Embedded Systems.
Proceedings of the Integrated Circuit and System Design, 2004
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
An Integrated FPGA Design Framework: Custom Designed FPGA Platform and Application Mapping Toolset Development.
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004
Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004
Proceedings of the Field Programmable Logic and Application, 2004
Mapping DSP Applications to a High-Performance Reconfigurable Coarse-Grain Data-Path.
Proceedings of the Field Programmable Logic and Application, 2004
Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004
Accelerating DSP Applications on a Mixed Granularity Platform with a New Reconfigurable Coarse-Grain Data-Path.
Proceedings of the 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 2004
Reducing memory accesses with a system-level design methodology in customized dynamic memory management.
Proceedings of the 2nd Workshop on Embedded Systems for Real-Time Multimedia, 2004
A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms.
Proceedings of the 2004 Design, 2004
Dynamic Memory Management Design Methodology for Reduced Memory Footprint in Multimedia and Wireless Network Applications.
Proceedings of the 2004 Design, 2004
2003
Data memory power optimization and performance exploration of embedded systems for implementing motion estimation algorithms.
Real Time Imaging, 2003
Designing Low Power Direct Digital Frequency Synthesizers.
Proceedings of the IFIP VLSI-SoC 2003, 2003
Proceedings of the Integrated Circuit and System Design, 2003
Power Optimization Methdology for Multimedia Applications Implementation on Reconfigurable Platforms.
Proceedings of the Integrated Circuit and System Design, 2003
A methodology for implementing FIR filters and CAD tool development for designing RNS-based systems.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Alternative Direct Digital Frequency Synthesizer architectures with reduced memory size.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Power-Efficient Implementations of Multimedia Applications on Reconfigurable Platforms.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003
2002
A fast and accurate delay dependent method for switching estimation of large combinational circuits.
J. Syst. Archit., 2002
Performance and Power Comparative Study of Discrete Wavelet Transform on Programmable Processors.
Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
Proceedings of the 2002 International Conference on Image Processing, 2002
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002
Proceedings of the 14th International Conference on Digital Signal Processing, 2002
Architecture Design of a Reconfigurable Multiplier for Flexible Coarse-Grain Implementations.
Proceedings of the Field-Programmable Logic and Applications, 2002
A Code Transformation-Based Methodology for Improving I-Cache Performance of DSP Applications.
Proceedings of the 2002 Design, 2002
2001
VLSI Design, 2001
A Probabilistic Power Estimation Method for Combinational Circuits Under Real Gate Delay Model.
VLSI Design, 2001
Memory Hierarchy Optimization of Multimedia Applications on Programmable Embedded Cores 1.
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
A CAD tool for architecture level exploration and automatic generation of RNS converters.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
On the implementation of a baseband processor for a portable dual mode DECT/GSM terminal.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Power, performance and area exploration of block matching algorithms mapped on programmable processors.
Proceedings of the 2001 International Conference on Image Processing, 2001
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001
Data and instruction memory exploration of embedded systems for multimedia applications.
Proceedings of the IEEE International Conference on Acoustics, 2001
2000
Reducing Power Consumption through Dynamic Frequency Scaling for a Class of Digital Receivers.
Proceedings of the Integrated Circuit Design, 2000
Data-Reuse and Parallel Embedded Architectures for Low-Power, Real-Time Multimedia Applications.
Proceedings of the Integrated Circuit Design, 2000
A methodology for the behavioral-level event-driven power management of digital receivers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
1999
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999
1998
Multiple-Valued Logic Voltage-Mode Storage Circuits Based On True-Single-Phase Clocked Logic.
Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998
1996
Transformation of Nested Loops into Uniform Recurrences and their Mapping to Regular Processor Arrays.
J. Circuits Syst. Comput., 1996
Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996
Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996
1993
A Systematic Methodology for Designing Multilevel Systolic Architectures.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993
Methodology for the Design of Signed-digit DSP Processors.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993
Proceedings of the IEEE International Conference on Acoustics, 1993
1992
Systematic development of architectures for multidimensional DSP using the residue number system.
Proceedings of the 1992 IEEE International Conference on Acoustics, 1992
1991
Mapping iterative algorithims on regular processor arrays without using uniform recurrent equations.
Microprocessing and Microprogramming, 1991
Direct mapping of nested loops on piecewise regular processor arrays.
Proceedings of the Algorithms and Parallel VLSI Architectures II, 1991