Thanos Stouraitis

According to our database1, Thanos Stouraitis authored at least 86 papers between 1985 and 2018.

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Awards

IEEE Fellow

IEEE Fellow 2007, "For contributions to high-performance digital signal processing architectures and computer arithmetic".

Timeline

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Bibliography

2018
Performance Analysis of Non-Orthogonal Multiple Access Under I/Q Imbalance.
IEEE Access, 2018

Outage probability of single carrier NOMA systems under I/Q imbalance.
Proceedings of the 2018 IEEE Wireless Communications and Networking Conference, 2018

Performance Analysis of Single Carrier Coherent and Noncoherent Modulation under I/Q Imbalance.
Proceedings of the 87th IEEE Vehicular Technology Conference, 2018

Outage probability of multi-carrier NOMA systems under joint I/Q imbalance.
Proceedings of the International Conference on Advanced Communication Technologies and Networking, 2018

2017
Application-specific processor for local-binary-patterns generation.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

Assessment of seven reconstruction methods for contemporary compressive sensing.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

Application specific design for digital beam-former (DBF).
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

Automatic detection of coronary artery disease (CAD) in an ECG signal.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

A novel secure conference communication in IoT devices based on memristors.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

2016
A High-Speed FPGA Implementation of an RSD-Based ECC Processor.
IEEE Trans. VLSI Syst., 2016

Editorial for QShine 2014 Special Issue.
MONET, 2016

Area-Throughput Trade-Offs for SHA-1 and SHA-256 Hash Functions' Pipelined Designs.
Journal of Circuits, Systems, and Computers, 2016

2015
A reliable and energy efficient IoT data transmission scheme for smart cities based on redundant residue based error correction coding.
Proceedings of the 12th Annual IEEE International Conference on Sensing, 2015

Low-complexity energy-efficient security approach for e-health applications based on physically unclonable functions of sensors.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

2014
Multifunction Residue Architectures for Cryptography.
IEEE Trans. on Circuits and Systems, 2014

An orthogonal wavelet division multiple-access processor architecture for LTE-advanced wireless/radio-over-fiber systems over heterogeneous networks.
EURASIP J. Adv. Sig. Proc., 2014

An RNS barrett modular multiplication architecture.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013
Efficient RNS Implementation of Elliptic Curve Point Multiplication Over ${\rm GF}(p)$.
IEEE Trans. VLSI Syst., 2013

Hardware-fault attack handling in RNS-based Montgomery multipliers.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

An RNS modular multiplication algorithm.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

2012
GF(2n) Montgomery multiplication using Polynomial Residue Arithmetic.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A novel implementation of sequential output based parallel processing - orthogonal wavelet division multiplexing for DAS on SDR platform.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

2011
A RNS Montgomery multiplication architecture.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2010
Modeling and exploiting spatial locality trade-offs in wavelet-based applications under varying resource requirements.
ACM Trans. Embedded Comput. Syst., 2010

Comparison of time and frequency domain interpolation implementations for MB-OFDM UWB transmitters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Optimal modulus sets for efficient residue-to-binary conversion using the New Chinese Remainder Theorems.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

2009
Exploiting Varying Resource Requirements in Wavelet-based Applications in Dynamic Execution Environments.
Signal Processing Systems, 2009

Spatial locality exploitation for runtime reordering of JPEG2000 wavelet data layouts.
ACM Trans. Design Autom. Electr. Syst., 2009

An RNS Implementation of an Fp Elliptic Curve Point Multiplier.
IEEE Trans. on Circuits and Systems, 2009

Design of a balanced 8-modulus RNS.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

Elliptic Curve Point Multiplication in GF(2n) using Polynomial Residue Arithmetic.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

2008
A frequency-domain interpolation implementation for OFDM transmitters.
Proceedings of the Third International Symposium on Wireless Pervasive Computing, 2008

2007
Large Dynamic Range RNS Systems and their Residue to Binary converters.
Journal of Circuits, Systems, and Computers, 2007

Analysis and design of a WLAN OFDM transmitter with digital filters.
Proceedings of the 3rd International Conference on Mobile Multimedia Communications, 2007

Content-Adaptive Wavelet-Based Scalable Video Coding.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Comparison of VLSI architectures for a WLAN OFDM transmitter with interpolation filters.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

Adaptive mapping to resource availability for dynamic wavelet-based applications.
Proceedings of the 2007 5th Workshop on Embedded Systems for Real-Time Multimedia, 2007

2006
Software-Controlled Scratchpad Mapping Strategies for Wavelet-Based Applications.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006

An RNS architecture of an Fp elliptic curve point multiplier.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Execution time comparison of lifting-based 2D wavelet transforms implementations on a VLIW DSP.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005
Hidden messages in heavy-tails: DCT-domain watermark detection using alpha-stable models.
IEEE Trans. Multimedia, 2005

Systolic algorithms and a memory-based design approach for a unified architecture for the computation of DCT/DST/IDCT/IDST.
IEEE Trans. on Circuits and Systems, 2005

Optimized memory requirements for wavelet-based scalable multimedia codecs.
J. Embedded Computing, 2005

2003
New power-of-2 RNS scaling scheme for cell-based IC design.
IEEE Trans. VLSI Syst., 2003

Power efficient data path synthesis of sum-of-products computations.
IEEE Trans. VLSI Syst., 2003

A computational technique and a VLSI architecture for digital pulse shaping in OFDM modems.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2002
Memory accesses reordering for interconnect power reduction in sum-of-products computations.
IEEE Trans. Signal Processing, 2002

A systolic array architecture for the discrete sine transform.
IEEE Trans. Signal Processing, 2002

VLSI architectures for the implementation of the Wigner distribution.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

A novel list-scheduling algorithm for the low-energy program execution.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Multi-voltage low power convolvers using the polynomial residue number system.
Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, 2002

2001
Operation-Saving VLSI Architectures for 3D Geometrical Transformations.
IEEE Trans. Computers, 2001

Signal activity and power consumption reduction using the logarithmic number system.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

A vector processor for 3-D geometrical transformations.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

A local wavelet transform implementation versus an optimal row-column algorithm for the 2D multilevel decomposition.
Proceedings of the 2001 International Conference on Image Processing, 2001

A wavelet-tree image coding system with efficient memory utilization.
Proceedings of the IEEE International Conference on Acoustics, 2001

Low-Power Properties of the Logarithmic Number System.
Proceedings of the 15th IEEE Symposium on Computer Arithmetic (Arith-15 2001), 2001

2000
Low power architectures for digital signal processing.
Journal of Systems Architecture, 2000

Logarithmic Number System for Low-Power Arithmetic.
Proceedings of the Integrated Circuit Design, 2000

Low power synthesis of sum-of-products computation (poster session).
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000

1999
Computation Reordering: A Novel Transformation for Low Power DSP Synthesis.
VLSI Design, 1999

Novel techniques for bus power consumption reduction in realizations of sum-of-product computation.
IEEE Trans. VLSI Syst., 1999

An efficient probabilistic method for logic circuits using real delay gate model.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Grouped-moduli residue number systems for fast signal processing.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

The VLSI implementation of a baseband receiver for DECT-based portable applications.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Novel high-radix residue number system multipliers and adders.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Low power synthesis of sum-of-product computation in DSP algorithms.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

1998
Trade-Off Analysis of a Low-Power Image Coding Algorithm.
VLSI Signal Processing, 1998

A novel algorithm for low-power image and video coding.
IEEE Trans. Circuits Syst. Video Techn., 1998

Novel codebook generation algorithms for vector quantization image compression.
Proceedings of the 1998 IEEE International Conference on Acoustics, 1998

Multiple-Valued Logic Voltage-Mode Storage Circuits Based On True-Single-Phase Clocked Logic.
Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998

Low-power implementation of discrete wavelet transform.
Proceedings of the 9th European Signal Processing Conference, 1998

1997
An operation-saving VLSI geometry engine core.
Proceedings of the 1997 IEEE International Conference on Acoustics, 1997

Area-time performance of VLSI FIR filter architectures based on residue arithmetic.
Proceedings of the 23rd EUROMICRO Conference '97, 1997

1995
Prime-factor DCT algorithms.
IEEE Trans. Signal Processing, 1995

On the computation of the prime factor DST.
Signal Processing, 1995

A Novel Algorithm for Multi-Operand Logarithmic Number System Addition and Subtraction Using Polynominal Approximation.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Alternative Architectures for the 2-D DCT Algorithm.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

1994
Systematic Design of Multi-Modulus/Multi-Function Residue Number System Processors.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

1993
Borrow: A Fault-Tolerance Scheme for Wavefront Array Processors.
IEEE Trans. Computers, 1993

Methodology for the Design of Signed-digit DSP Processors.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

Full Adder-based Inner Product Step Processors for Residue and Quadratic Residue Number Systems.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

Systematic design of full adder-based architectures for convolution.
Proceedings of the IEEE International Conference on Acoustics, 1993

1992
Decomposition of Complex Multipliers Using Polynomial Encoding.
IEEE Trans. Computers, 1992

1991
Multiplication of complex numbers encoded as polynomials.
VLSI Signal Processing, 1991

1985
A Radix-4FFT Using Complex RNS Arithmetic.
IEEE Trans. Computers, 1985


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