Thanos Stouraitis

IEEE Consumer Electron. Mag., January, 2024

2023

Number Systems for Deep Neural Network Architectures: A Survey.

[BibT_eX]

[DOI]

Ghada Alsuhli

Vasileios Sakellariou

CoRR, 2023

Gradient Estimation for Ultra Low Precision POT and Additive POT Quantization.

[BibT_eX]

[DOI]

Athanasios Stouraitis

IEEE Access, 2023

Proactive Random-Forest Autoscaler for Microservice Resource Allocation.

[BibT_eX]

[DOI]

Lamees M. Al Qassem

Ernesto Damiani

Ibrahim Abe M. Elfadel

IEEE Access, 2023

EACNN: Efficient CNN Accelerator Utilizing Linear Approximation and Computation Reuse.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Efficient CNN Hardware Architecture Based on Linear Approximation and Computation Reuse Technique.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Microelectronics, 2023

Efficient Mux-Based Multiplier for MAC Unit.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Microelectronics, 2023

A Regularization Approach to Maximize Common Sub-Expressions in Neural Network Weights.

[BibT_eX]

[DOI]

Emmanouil Kavvousanos

Ioannis Kouretas

Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023

Dynamic Monitoring of Probiotics Effect in Parkinson's Disease Patients via Swarm Decomposition and Bispectral Analysis of Electrogastrograms.

[BibT_eX]

[DOI]

Vasileios S. Charisis

Stelios Hadjidimitriou

Leontios J. Hadjileontiadis

Proceedings of the 45th Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2023

Classification of children with ADHD through task-related EEG recordings via Swarm-Decomposition-based Phase Locking Value.

[BibT_eX]

[DOI]

Efstratia Ganiti-Roumeliotou

Leontios J. Hadjileontiadis

Proceedings of the 45th Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2023

OSμS: An Open-Source Microservice Prototyping Platform.

[BibT_eX]

[DOI]

Lamees M. Al Qassem

Ernesto Damiani

Ibrahim Abe M. Elfadel

Proceedings of the IEEE International Conference on Cloud Computing Technology and Science, 2023

A multiplier-Free RNS-Based CNN accelerator exploiting bit-Level sparsity.

[BibT_eX]

[DOI]

Proceedings of the 30th IEEE Symposium on Computer Arithmetic, 2023

Improving Residue-Level Sparsity in RNS-based Neural Network Hardware Accelerators via Regularization.

[BibT_eX]

[DOI]

Emmanouil Kavvousanos

Proceedings of the 30th IEEE Symposium on Computer Arithmetic, 2023

Modified Logarithmic Multiplication Approximation for Machine Learning.

[BibT_eX]

[DOI]

Ioannis Kouretas

Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023

2022

FPGAaaS: A Survey of Infrastructures and Systems.

[BibT_eX]

[DOI]

IEEE Trans. Serv. Comput., 2022

A High-performance RNS LSTM block.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Approximate Logarithmic Multiplier For Convolutional Neural Network Inference With Computational Reuse.

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022

2021

Performance Analysis of Coherent and Noncoherent Modulation Under I/Q Imbalance Effects.

[BibT_eX]

[DOI]

IEEE Access, 2021

On Reducing the Number of Multiplications in RNS-based CNN Accelerators.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE International Conference on Electronics, 2021

2020

Computational Power Evaluation for Energy-Constrained Wireless Communications Systems.

[BibT_eX]

[DOI]

IEEE Open J. Commun. Soc., 2020

A Remote FPGA Laboratory as a Cloud Microservice.

[BibT_eX]

[DOI]

Lamees M. Al Qassem

Ernesto Damiani

Ibrahim Abe M. Elfadel

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019

Radio-Frequency Front-End Impairments: Performance Degradation in Nonorthogonal Multiple Access Communication Systems.

[BibT_eX]

[DOI]

Arafat Al-Dweik

IEEE Veh. Technol. Mag., 2019

2018

Performance Analysis of Non-Orthogonal Multiple Access Under I/Q Imbalance.

[BibT_eX]

[DOI]

IEEE Access, 2018

Outage probability of single carrier NOMA systems under I/Q imbalance.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Wireless Communications and Networking Conference, 2018

Performance Analysis of Single Carrier Coherent and Noncoherent Modulation under I/Q Imbalance.

[BibT_eX]

[DOI]

Proceedings of the 87th IEEE Vehicular Technology Conference, 2018

Outage probability of multi-carrier NOMA systems under joint I/Q imbalance.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Advanced Communication Technologies and Networking, 2018

2017

Application-specific processor for local-binary-patterns generation.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

Assessment of seven reconstruction methods for contemporary compressive sensing.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

Application specific design for digital beam-former (DBF).

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

Automatic detection of coronary artery disease (CAD) in an ECG signal.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

A novel secure conference communication in IoT devices based on memristors.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

2016

A High-Speed FPGA Implementation of an RSD-Based ECC Processor.

[BibT_eX]

[DOI]

Hamad Marzouqi

Mahmoud Al-Qutayri

Khaled Salah

IEEE Trans. Very Large Scale Integr. Syst., 2016

Editorial for QShine 2014 Special Issue.

[BibT_eX]

[DOI]

Mob. Networks Appl., 2016

Area-Throughput Trade-Offs for SHA-1 and SHA-256 Hash Functions' Pipelined Designs.

[BibT_eX]

[DOI]

Harris E. Michail

George Athanasiou

Vasilios I. Kelefouras

George Theodoridis

Costas E. Goutis

J. Circuits Syst. Comput., 2016

2015

A reliable and energy efficient IoT data transmission scheme for smart cities based on redundant residue based error correction coding.

[BibT_eX]

[DOI]

Proceedings of the 12th Annual IEEE International Conference on Sensing, 2015

Low-complexity energy-efficient security approach for e-health applications based on physically unclonable functions of sensors.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Conference on Electronics, 2015

2014

Multifunction Residue Architectures for Cryptography.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2014

An orthogonal wavelet division multiple-access processor architecture for LTE-advanced wireless/radio-over-fiber systems over heterogeneous networks.

[BibT_eX]

[DOI]

Chinmaya Mahapatra

Victor C. M. Leung

EURASIP J. Adv. Signal Process., 2014

An RNS barrett modular multiplication architecture.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013

Efficient RNS Implementation of Elliptic Curve Point Multiplication Over ${\rm GF}(p)$.

[BibT_eX]

[DOI]

Mohammad Esmaeildoust

Hamid Javashi

Keivan Navi

IEEE Trans. Very Large Scale Integr. Syst., 2013

Hardware-fault attack handling in RNS-based Montgomery multipliers.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

An RNS modular multiplication algorithm.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE International Conference on Electronics, 2013

2012

GF(2n) Montgomery multiplication using Polynomial Residue Arithmetic.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A novel implementation of sequential output based parallel processing - orthogonal wavelet division multiplexing for DAS on SDR platform.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

2011

A RNS Montgomery multiplication architecture.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2010

Modeling and exploiting spatial locality trade-offs in wavelet-based applications under varying resource requirements.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2010

Comparison of time and frequency domain interpolation implementations for MB-OFDM UWB transmitters.

[BibT_eX]

[DOI]

Dorina Thanou

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Optimal modulus sets for efficient residue-to-binary conversion using the New Chinese Remainder Theorems.

[BibT_eX]

[DOI]

Narendran Narayanaswamy

Proceedings of the 17th IEEE International Conference on Electronics, 2010

2009

Exploiting Varying Resource Requirements in Wavelet-based Applications in Dynamic Execution Environments.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2009

Spatial locality exploitation for runtime reordering of JPEG2000 wavelet data layouts.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2009

An RNS Implementation of an Fp Elliptic Curve Point Multiplier.

[BibT_eX]

[DOI]

Athanasios P. Kakarountas

Apostolos P. Fournaris

Harris E. Michail

IEEE Trans. Circuits Syst. I Regul. Pap., 2009

Design of a balanced 8-modulus RNS.

[BibT_eX]

[DOI]

Mohammad Abdallah

Proceedings of the 16th IEEE International Conference on Electronics, 2009

Elliptic Curve Point Multiplication in GF(2n) using Polynomial Residue Arithmetic.

[BibT_eX]

[DOI]

Athanasios Kakarountas

Proceedings of the 16th IEEE International Conference on Electronics, 2009

2008

A frequency-domain interpolation implementation for OFDM transmitters.

[BibT_eX]

[DOI]

Proceedings of the Third International Symposium on Wireless Pervasive Computing, 2008

2007

Large Dynamic Range RNS Systems and their Residue to Binary converters.

[BibT_eX]

[DOI]

Mohammad Abdallah

J. Circuits Syst. Comput., 2007

Analysis and design of a WLAN OFDM transmitter with digital filters.

[BibT_eX]

[DOI]

Pavlos Kolovos

Proceedings of the 3rd International Conference on Mobile Multimedia Communications, 2007

Content-Adaptive Wavelet-Based Scalable Video Coding.

[BibT_eX]

[DOI]

Dionisis Athanasopoulos

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Comparison of VLSI architectures for a WLAN OFDM transmitter with interpolation filters.

[BibT_eX]

[DOI]

Pavlos Kolovos

Proceedings of the 14th IEEE International Conference on Electronics, 2007

Adaptive mapping to resource availability for dynamic wavelet-based applications.

[BibT_eX]

[DOI]

Proceedings of the 2007 5th Workshop on Embedded Systems for Real-Time Multimedia, 2007

2006

Software-Controlled Scratchpad Mapping Strategies for Wavelet-Based Applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE Workshop on Signal Processing Systems, 2006

An RNS architecture of an Fp elliptic curve point multiplier.

[BibT_eX]

[DOI]

Apostolos P. Fournaris

Athanasios Kakarountas

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Execution time comparison of lifting-based 2D wavelet transforms implementations on a VLIW DSP.

[BibT_eX]

[DOI]

Yiannis Andreopoulos

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005

Hidden messages in heavy-tails: DCT-domain watermark detection using alpha-stable models.

[BibT_eX]

[DOI]

Alexia Briassouli

Panagiotis Tsakalides

Athanasios Stouraitis

IEEE Trans. Multim., 2005

Systolic algorithms and a memory-based design approach for a unified architecture for the computation of DCT/DST/IDCT/IDST.

[BibT_eX]

[DOI]

Doru-Florin Chiper

M. N. Shanmukha Swamy

M. Omair Ahmad

IEEE Trans. Circuits Syst. I Regul. Pap., 2005

Optimized memory requirements for wavelet-based scalable multimedia codecs.

[BibT_eX]

[DOI]

J. Embed. Comput., 2005

2003

New power-of-2 RNS scaling scheme for cell-based IC design.

[BibT_eX]

[DOI]

Uwe Meyer-Bäse

IEEE Trans. Very Large Scale Integr. Syst., 2003

Power efficient data path synthesis of sum-of-products computations.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2003

A computational technique and a VLSI architecture for digital pulse shaping in OFDM modems.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2002

Memory accesses reordering for interconnect power reduction in sum-of-products computations.

[BibT_eX]

[DOI]

Konstantinos Masselos

IEEE Trans. Signal Process., 2002

A systolic array architecture for the discrete sine transform.

[BibT_eX]

[DOI]

IEEE Trans. Signal Process., 2002

VLSI architectures for the implementation of the Wigner distribution.

[BibT_eX]

[DOI]

D. Zografos

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

A novel list-scheduling algorithm for the low-energy program execution.

[BibT_eX]

[DOI]

G. Sinevriotis

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Multi-voltage low power convolvers using the polynomial residue number system.

[BibT_eX]

[DOI]

Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, 2002

2001

Operation-Saving VLSI Architectures for 3D Geometrical Transformations.

[BibT_eX]

[DOI]

George Diamantakos

IEEE Trans. Computers, 2001

Signal activity and power consumption reduction using the logarithmic number system.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

A vector processor for 3-D geometrical transformations.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

A local wavelet transform implementation versus an optimal row-column algorithm for the 2D multilevel decomposition.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Conference on Image Processing, 2001

VLSI architectures for blind equalization based on fractional-order statistics.

[BibT_eX]

[DOI]

J. Dagres

Panagiotis Tsakalides

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

A wavelet-tree image coding system with efficient memory utilization.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 2001

Low-Power Properties of the Logarithmic Number System.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE Symposium on Computer Arithmetic (Arith-15 2001), 2001

2000

Low power architectures for digital signal processing.

[BibT_eX]

[DOI]

J. Syst. Archit., 2000

Logarithmic Number System for Low-Power Arithmetic.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit Design, 2000

Low power synthesis of sum-of-products computation (poster session).

[BibT_eX]

[DOI]

Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000

A hybrid image compression algorithm based on fractal coding and wavelet transform.

[BibT_eX]

[DOI]

loannis Andreopoulos

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

High-radix residue number system forward and inverse converters.

[BibT_eX]

[DOI]

Proceedings of the 2000 7th IEEE International Conference on Electronics, 2000

Development of a power efficient image coding algorithm based on integer wavelet transform.

[BibT_eX]

[DOI]

I. Andreopoulos

Proceedings of the 2000 7th IEEE International Conference on Electronics, 2000

1999

Computation Reordering: A Novel Transformation for Low Power DSP Synthesis.

[BibT_eX]

[DOI]

VLSI Design, 1999

Novel techniques for bus power consumption reduction in realizations of sum-of-product computation.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 1999

An efficient probabilistic method for logic circuits using real delay gate model.

[BibT_eX]

[DOI]

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Grouped-moduli residue number systems for fast signal processing.

[BibT_eX]

[DOI]

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

The VLSI implementation of a baseband receiver for DECT-based portable applications.

[BibT_eX]

[DOI]

Adonios Thanailakis

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Novel high-radix residue number system multipliers and adders.

[BibT_eX]

[DOI]

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Low power synthesis of sum-of-product computation in DSP algorithms.

[BibT_eX]

[DOI]

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Defect detection and classification on web textile fabric using multiresolution decomposition and neural networks.

[BibT_eX]

[DOI]

Radovan Stojanovic

Panagiotis Mitropoulos

Christos Koulamas

Stavros A. Koubias

George D. Papadopoulos

Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

1998

Trade-Off Analysis of a Low-Power Image Coding Algorithm.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 1998

A novel algorithm for low-power image and video coding.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. Video Technol., 1998

A VLSI architecture for fast and accurate floating-point sine/cosine evaluation.

[BibT_eX]

[DOI]

Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

A very-long instruction word digital signal processor based on the logarithmic number system.

[BibT_eX]

[DOI]

Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

Novel codebook generation algorithms for vector quantization image compression.

[BibT_eX]

[DOI]

Konstantinos Masselos

Costas E. Goutis

Proceedings of the 1998 IEEE International Conference on Acoustics, 1998

Multiple-Valued Logic Voltage-Mode Storage Circuits Based On True-Single-Phase Clocked Logic.

[BibT_eX]

[DOI]

Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998

Low-power implementation of discrete wavelet transform.

[BibT_eX]

[DOI]

Proceedings of the 9th European Signal Processing Conference, 1998

1997

An operation-saving VLSI geometry engine core.

[BibT_eX]

[DOI]

George Diamantakos

Proceedings of the 1997 IEEE International Conference on Acoustics, 1997

Area-time performance of VLSI FIR filter architectures based on residue arithmetic.

[BibT_eX]

[DOI]

Proceedings of the 23rd EUROMICRO Conference '97, 1997

1996

Low-power image decoding using fractals.

[BibT_eX]

[DOI]

Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996

A parallel image compression scheme based on fractal coding and vector quantization.

[BibT_eX]

[DOI]

Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996

Efficient algorithms and VLSI architectures for trigonometric functions in the logarithmic number system based on the subtraction function.

[BibT_eX]

[DOI]

E. N. Malamas

Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996

Coding wavelet coefficients of images.

[BibT_eX]

[DOI]

Chrissavgi Dre

Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996

1995

Prime-factor DCT algorithms.

[BibT_eX]

[DOI]

IEEE Trans. Signal Process., 1995

On the computation of the prime factor DST.

[BibT_eX]

[DOI]

Signal Process., 1995

A Novel Algorithm for Multi-Operand Logarithmic Number System Addition and Subtraction Using Polynominal Approximation.

[BibT_eX]

[DOI]

I. Orginos

Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Alternative Architectures for the 2-D DCT Algorithm.

[BibT_eX]

[DOI]

Chrissavgi Dre

Anna Tatsaki

Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

1994

Systematic Design of Multi-Modulus/Multi-Function Residue Number System Processors.

[BibT_eX]

[DOI]

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

1993

Borrow: A Fault-Tolerance Scheme for Wavefront Array Processors.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1993

Methodology for the Design of Signed-digit DSP Processors.

[BibT_eX]

Dimitrios Soudris

Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

Full Adder-based Inner Product Step Processors for Residue and Quadratic Residue Number Systems.

[BibT_eX]

Seon Wook Kim

Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

Systematic design of full adder-based architectures for convolution.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 1993

1992

Decomposition of Complex Multipliers Using Polynomial Encoding.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1992

Systematic development of architectures for multidimensional DSP using the residue number system.

[BibT_eX]

[DOI]

Dimitrios Soudris

Proceedings of the 1992 IEEE International Conference on Acoustics, 1992

1991

Multiplication of complex numbers encoded as polynomials.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 1991

1989

A hybrid floating-point/logarithmic number system digital signal processor.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 1989

A complex DSP processor using polynomial encoding.

[BibT_eX]

[DOI]

Zarir B. Sarkari

Proceedings of the IEEE International Conference on Acoustics, 1989

1988

Floating-point to logarithmic encoder error analysis.

[BibT_eX]

[DOI]

Fred J. Taylor

IEEE Trans. Computers, 1988

1985

A Radix-4FFT Using Complex RNS Arithmetic.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1985

A reconfigurable systolic primitive processor for signal processing.

[BibT_eX]

[DOI]