Adonios Thanailakis

According to our database1, Adonios Thanailakis authored at least 77 papers between 1986 and 2010.

Collaborative distances :
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2010
A Novel Allocation Methodology for Partial and Dynamic Bitstream Generation for FPGA Architectures.
Journal of Circuits, Systems, and Computers, 2010

2008
A CAD System for Modeling and Simulation of Computer Networks Using Cellular Automata.
IEEE Trans. Systems, Man, and Cybernetics, Part C, 2008

A Full-Adder-Based Methodology for the Design of Scaling Operation in Residue Number System.
IEEE Trans. on Circuits and Systems, 2008

Designing a General-Purpose Interconnection Architecture for Field Programmable Gate Arrays.
J. Low Power Electronics, 2008

2007
Systematic methodology for exploration of performance - Energy trade-offs in network applications using Dynamic Data Type refinement.
Journal of Systems Architecture, 2007

Architecture design of a coarse-grain reconfigurable multiply-accumulate unit for data-intensive applications.
Integration, 2007

Systematic methodology for designing low power direct digital frequency synthesisers.
IET Circuits, Devices & Systems, 2007

A Memory Hierarchical Layer Assigning and Prefetching Technique to Overcome the Memory Performance/Energy Bottleneck
CoRR, 2007

Designing Heterogeneous FPGAs with Multiple SBs.
Proceedings of the Reconfigurable Computing: Architectures, 2007

2006
Behavioral-Level Performance and Power Exploration of Data-Intensive Applications Mapped on Programmable Processors.
VLSI Signal Processing, 2006

A combined DMA and application-specific prefetching approach for tackling the memory latency bottleneck.
IEEE Trans. VLSI Syst., 2006

Reducing memory fragmentation in network applications with dynamic memory allocators optimized for performance.
Computer Communications, 2006

Efficient Power Management Strategy of FPGAs Using a Novel Placement Technique.
Proceedings of the IFIP VLSI-SoC 2006, 2006

Designing Alternative FPGA Implementations Using Spatial Data from Hardware Resources.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

A novel methodology for designing high-performance and low-power FPGA interconnection targeting DSP applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Platform-based FPGA architecture: designing high-performance and low-power routing structure for realizing DSP applications.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

A novel methodology for designing high-performance and low-energy FPGA routing architecture.
Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, 2006

Dynamic data type refinement methodology for systematic performance-energy design exploration of network applications.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
Substrate current and degradation of n-channel polycrystalline silicon thin-film transistors.
Microelectronics Reliability, 2005

Memory power optimization of hardware implementations of multimedia applications onto FPGA platforms.
J. Embedded Computing, 2005

A Novel Division Algorithm and Architectures for Parallel and Sequential Processing.
Journal of Circuits, Systems, and Computers, 2005

A Novel FPGA Architecture and an Integrated Framework of CAD Tools for Implementing Applications.
IEICE Transactions, 2005

A cellular automaton for the propagation of circular fronts and its applications.
Eng. Appl. of AI, 2005

A fault-tolerant message passing algorithm and its hardware implementation.
Advances in Engineering Software, 2005

Reducing Memory Fragmentation with Performance-Optimized Dynamic Memory Allocators in Network Applications.
Proceedings of the Wired/Wireless Internet Communications, Third International Conference, 2005

A Modified Spiral Search Algorithm and its Embedded Hardware Implementation.
Proceedings of the International Enformatika Conference, 2005

Improving the Memory Bandwidth Utilization Using Loop Transformations.
Proceedings of the Integrated Circuit and System Design, 2005

A modified spiral search motion estimation algorithm and its embedded system implementation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

DAGGER: A Novel Generic Methodology for FPGA Bitstream Generation and Its Software Tool Implementation.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

An Integrated Framework for Architecture Level Exploration of Reconfigurable Platform.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

A Low-Energy FPGA: Architecture Design and Software-Supported Design Flow.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

A Memory Hierarchical Layer Assigning and Prefetching Technique to Overcome the Memory Performance/Energy Bottleneck.
Proceedings of the 2005 Design, 2005

AMDREL: a novel low-energy FPGA architecture and supporting CAD tool design flow.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Design and simulation of a nanoelectronic single-electron universal Control-Control-Not gate.
Microelectronics Journal, 2004

Design of Energy Efficient Wireless Networks Using Dynamic Data Type Refinement Methodology.
Proceedings of the Wired/Wireless Internet Communications, Second International Conference, 2004

Power, Performance and Area Exploration for Data Memory Assignment of Multimedia Applications.
Proceedings of the Computer Systems: Architectures, 2004

A reusable IP FFT core for DSP applications.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

An Integrated FPGA Design Framework: Custom Designed FPGA Platform and Application Mapping Toolset Development.
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

A Novel FPGA Configuration Bitstream Generation Algorithm and Tool Development.
Proceedings of the Field Programmable Logic and Application, 2004

2003
Data memory power optimization and performance exploration of embedded systems for implementing motion estimation algorithms.
Real-Time Imaging, 2003

A CAD system for the construction and VLSI implementation of Cellular Automata algorithms using VHDL.
Microprocessors and Microsystems, 2003

A cellular automaton model for the study of DNA sequence evolution.
Comp. in Bio. and Med., 2003

Designing Low Power Direct Digital Frequency Synthesizers.
Proceedings of the IFIP VLSI-SoC 2003, 2003

FPGA Architecture Design and Toolset for Logic Implementation.
Proceedings of the Integrated Circuit and System Design, 2003

Power Optimization Methdology for Multimedia Applications Implementation on Reconfigurable Platforms.
Proceedings of the Integrated Circuit and System Design, 2003

A methodology for implementing FIR filters and CAD tool development for designing RNS-based systems.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Alternative Direct Digital Frequency Synthesizer architectures with reduced memory size.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Power-Efficient Implementations of Multimedia Applications on Reconfigurable Platforms.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

2002
A fast and accurate delay dependent method for switching estimation of large combinational circuits.
Journal of Systems Architecture, 2002

A cellular automaton methodology for the simulation of integrated circuit fabrication processes.
Future Generation Comp. Syst., 2002

Architecture Design of a Reconfigurable Multiplier for Flexible Coarse-Grain Implementations.
Proceedings of the Field-Programmable Logic and Applications, 2002

2001
The circuit design of multiple-valued logic voltage-mode adders.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

A CAD tool for architecture level exploration and automatic generation of RNS converters.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Power, performance and area exploration of block matching algorithms mapped on programmable processors.
Proceedings of the 2001 International Conference on Image Processing, 2001

2000
Data-Reuse and Parallel Embedded Architectures for Low-Power, Real-Time Multimedia Applications.
Proceedings of the Integrated Circuit Design, 2000

A methodology for the behavioral-level event-driven power management of digital receivers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Low power design of a multi-mode transceiver.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Designing RNS and QRNS full adder based converters.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1999
The VLSI implementation of a baseband receiver for DECT-based portable applications.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

1998
Non-linear Hybrid Cellular Automata as Pseudorandom Pattern Generators for VLSI Systems.
VLSI Design, 1998

Multiple-Valued Logic Voltage-Mode Storage Circuits Based On True-Single-Phase Clocked Logic.
Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998

1997
Collision-free path planning for a diamond-shaped robot using two-dimensional cellular automata.
IEEE Trans. Robotics and Automation, 1997

Geometrical Shape Recognition Using a Cellular Automaton Architecture and its VLSI Implementation.
Real-Time Imaging, 1997

An efficient algorithm for the largest empty figure problem based on a 2D cellular automaton architecture.
Image Vision Comput., 1997

1996
A cellular automaton for the determination of the mean velocity of moving objects and its VLSI implementation.
Pattern Recognition, 1996

A new hardware module for automated visual inspection based on a cellular automaton architecture.
Journal of Intelligent and Robotic Systems, 1996

A hybrid cellular automaton/neural network classifier for multi-valued patterns and its VLSI implementation.
Integration, 1996

1995
A Parallel Skeletonization Algorithm Based on Two-Dimensional Cellular Automata and its VLSI Implementation.
Real-Time Imaging, 1995

1994
A new, cellular automaton-based, nearest neighbor pattern classifier and its VLSI implementation.
IEEE Trans. VLSI Syst., 1994

A modified discrete Fourier-cosine transform algorithm and its VLSI implementation.
Microprocessors and Microsystems - Embedded Hardware Design, 1994

Bit-serial VLSI sorter with high reliability specifications.
Microprocessing and Microprogramming, 1994

1993
2-Dimensional minimum cost path planning using a cellular automaton architecture.
Integration, 1993

1992
Hierarchical Cellular Automata structures.
Parallel Computing, 1992

1989
Synchronization of D. Parkinsonasynchronous concurrent processes using cellular automata.
Parallel Computing, 1989

Algebraic Theory of Bounded One-dimensional Cellular Automata.
Complex Systems, 1989

1986
Group Properties of Cellular Automata and VLSI Applications.
IEEE Trans. Computers, 1986

Analysis of Bounded Linear Cellular Automata Based on a Method of Image Charges.
J. Comput. Syst. Sci., 1986


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