Íñigo Ugarte

Orcid: 0000-0003-2586-2339

According to our database1, Íñigo Ugarte authored at least 12 papers between 2003 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2021
Pre-Silicon FEC Decoding Verification on SoC FPGAs.
IEEE Commun. Lett., 2021

2019
OpenMP Dynamic Device Offloading in Heterogeneous Platforms.
Proceedings of the OpenMP: Conquering the Full Hardware Spectrum, 2019

Design Space Exploration in Heterogeneous Platforms Using OpenMP.
Proceedings of the XXXIV Conference on Design of Circuits and Integrated Systems, 2019

2012
Towards automated implementation of adaptive systems from abstract SystemC specifications - From SystemC adaptive processes to embedded software and to synthesizable hardware descriptions.
Des. Autom. Embed. Syst., 2012

2008
Optimized coverage-directed random simulation.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2008

2006
Assertion checking of control dominated systems with nonlinear solvers.
Proceedings of the 4th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2006), 2006

Assertion-based Verification of Behavioral Descriptions with Non-linear Solver.
Proceedings of the Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, 2006

2005
Verification of Embedded Systems Based on Interval Analysis.
Int. J. Parallel Program., 2005

Extended abstract: polynomial model-based evaluation of the branch coverage metric for functional verification of hardware systems.
Proceedings of the 3rd ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2005), 2005

Assertion Checking of Behavioral Descriptions with Non-linear Solver.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Formal meaning of coverage metrics in simulation-based hardware design verification.
Proceedings of the Tenth IEEE International High-Level Design Validation and Test Workshop 2005, Napa Valley, CA, USA, November 30, 2005

2003
Functional vector generation for assertion-based verification at behavioral level using interval analysis.
Proceedings of the Eighth IEEE International High-Level Design Validation and Test Workshop 2003, 2003


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