Isuru Nawinne

Orcid: 0009-0001-4760-3533

According to our database1, Isuru Nawinne authored at least 17 papers between 2013 and 2026.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
Synthetic Cardiac MRI Image Generation using Deep Generative Models.
CoRR, March, 2026

SNAP-V: A RISC-V SoC with Configurable Neuromorphic Acceleration for Small-Scale Spiking Neural Networks.
CoRR, March, 2026

Balancing Fidelity, Utility, and Privacy in Synthetic Cardiac MRI Generation: A Comparative Study.
CoRR, March, 2026

2025
AICRN: Attention-Integrated Convolutional Residual Network for Interpretable Electrocardiogram Analysis.
CoRR, August, 2025

Inductive transfer learning from regression to classification in ECG analysis.
CoRR, August, 2025

AI-assisted radiographic analysis in detecting alveolar bone-loss severity and patterns.
CoRR, June, 2025

Integrated Programming and Compiler Toolchain for Swarm Robotic Systems.
Proceedings of the 2025 IEEE 19th International Conference on Industrial and Information Systems (ICIIS), 2025

2024
Multimodal Deep Convolutional Neural Network Pipeline for AI-Assisted Early Detection of Oral Cancer.
IEEE Access, 2024

2023
Mixed-Reality Based Multi-Agent Robotics Framework for Artificial Swarm Intelligence Experiments.
IEEE Access, 2023

RV32IMF Five-Stage Pipeline Implementation with Interrupt and Random Number Generation Units.
Proceedings of the 17th IEEE International Conference on Industrial and Information Systems, 2023

2019
An Ensemble Learning Approach for Electrocardiogram Sensor Based Human Emotion Recognition.
Sensors, 2019

Non-contact Infant Sleep Apnea Detection.
Proceedings of the 14th Conference on Industrial and Information Systems, 2019

2016
Hardware accelerated cache design space exploration for application specific MPSoCs.
PhD thesis, 2016

Switchable cache: utilising dark silicon for application specific cache optimisations.
IET Comput. Digit. Tech., 2016

2015
Exploring Multilevel Cache Hierarchies in Application Specific MPSoCs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

2014
Hardware-based fast exploration of cache hierarchies in application specific MPSoCs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Latency-constrained binding of data flow graphs to energy conscious GALS-based MPSoCs.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013


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