Josef Schneider

According to our database, Josef Schneider authored at least 6 papers between 2013 and 2015.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2015

Speeding up single pass simulation of PLRUt caches.

Josef Schneider, Jorgen Peddersen, Sri Parameswaran

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014

Hardware-based fast exploration of cache hierarchies in application specific MPSoCs.

Isuru Nawinne, Josef Schneider, Haris Javaid, Sri Parameswaran

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

MASH{fifo}: A Hardware-Based Multiple Cache Simulator for Rapid FIFO Cache Analysis.

Josef Schneider, Jorgen Peddersen, Sri Parameswaran

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

A scorchingly fast FPGA-based Precise L1 LRU cache simulator.

Josef Schneider, Jorgen Peddersen, Sri Parameswaran

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013

Analyzing the thermal hotspots in FPGA-based embedded systems.

Hussam Amrouch, Thomas Ebi, Josef Schneider, Sridevan Parameswaran, Jörg Henkel

Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

An extremely compact JPEG encoder for adaptive embedded systems.

Josef Schneider, Sri Parameswaran

Proceedings of the Design, Automation and Test in Europe, 2013