Sri Parameswaran

IACR Trans. Cryptogr. Hardw. Embed. Syst., 2024

2023

ApproxTrain: Fast Simulation of Approximate Multipliers for DNN Training and Inference.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023

Cross Layer Design Using HW/SW Co-Design and HLS to Accelerate Chaining in Genomic Analysis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., September, 2023

Special Issue: "Approximation at the Edge".

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., July, 2023

Invited: Algorithms and Architectures for Accelerating Long Read Sequence Analysis.

[BibT_eX]

[DOI]

Hasindu Gamaarachchi

Kisaru Liyanage

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

FPGA Based Countermeasures against Side Channel Attacks on Block Ciphers.

[BibT_eX]

[DOI]

Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022

A Power to Pulse Width Modulation Sensor for Remote Power Analysis Attacks.

[BibT_eX]

[DOI]

IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022

VITI: A Tiny Self-Calibrating Sensor for Power-Variation Measurement in FPGAs.

[BibT_eX]

[DOI]

IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022

Efficient Real-Time Selective Genome Sequencing on Resource-Constrained Devices.

[BibT_eX]

[DOI]

CoRR, 2022

Fast Selective Flushing to Mitigate Contention-based Cache Timing Attacks.

[BibT_eX]

[DOI]

CoRR, 2022

HWST128: complete memory safety accelerator on RISC-V with metadata compression.

[BibT_eX]

[DOI]

Hsu-Kang Dow

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

FaSe: fast selective flushing to mitigate contention-based cache timing attacks.

[BibT_eX]

[DOI]

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021

COPS: A complete oblivious processing system.

[BibT_eX]

[DOI]

Microprocess. Microsystems, September, 2021

QuadSeal: Quadruple Balancing to Mitigate Power Analysis Attacks with Variability Effects and Electromagnetic Fault Injection Attacks.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2021

UCloD: Small Clock Delays to Mitigate Remote Power Analysis Attacks.

[BibT_eX]

[DOI]

IEEE Access, 2021

SHORE: Hardware/Software Method for Memory Safety Acceleration on RISC-V.

[BibT_eX]

[DOI]

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

Approximate Computing for ML: State-of-the-art, Challenges and Visions.

[BibT_eX]

[DOI]

Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020

Hardware Trojan Mitigation in Pipelined MPSoCs.

[BibT_eX]

[DOI]

Vikkitharan Gnanasambandapillai

ACM Trans. Design Autom. Electr. Syst., 2020

Cache Friendly Optimisation of de Bruijn Graph Based Local Re-Assembly in Variant Calling.

[BibT_eX]

[DOI]

IEEE ACM Trans. Comput. Biol. Bioinform., 2020

Fast Short Read De-Novo Assembly Using Overlap-Layout-Consensus Approach.

[BibT_eX]

[DOI]

IEEE ACM Trans. Comput. Biol. Bioinform., 2020

FINDER: Find Efficient Parallel Instructions for ASIPs to Improve Performance of Large Applications.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

SIMF: Single-Instruction Multiple-Flush Mechanism for Processor Temporal Isolation.

[BibT_eX]

[DOI]

Bradley Hopkins

CoRR, 2020

GPU accelerated adaptive banded event alignment for rapid comparative nanopore signal analysis.

[BibT_eX]

[DOI]

BMC Bioinform., 2020

A Sub-Range Error Characterization based Selection Methodology for Approximate Arithmetic Units.

[BibT_eX]

[DOI]

Proceedings of the 33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems, 2020

Seed-and-Vote based In-Memory Accelerator for DNA Read Mapping.

[BibT_eX]

[DOI]

Ann Franchesca Laguna

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

LFTSM: Lightweight and Fully Testable SEU Mitigation System for Xilinx Processor-Based SoCs.

[BibT_eX]

[DOI]

Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020

REALM: Reduced-Error Approximate Log-based Integer Multiplier.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

WEID: Worst-case Error Improvement in Approximate Dividers.

[BibT_eX]

[DOI]

Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019

SWARAM: Portable Energy and Cost Efficient Embedded System for Genomic Processing.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2019

Pairwise alignment of nucleotide sequences using maximal exact matches.

[BibT_eX]

[DOI]

Arash Bayat

Bruno Gaëta

BMC Bioinform., 2019

SCRIP: Secure Random Clock Execution on Soft Processor Systems to Mitigate Power-based Side Channel Attacks.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2019

Hardware Trojan Detection and Recovery in MPSoCs via On-line Application Specific Testing.

[BibT_eX]

[DOI]

Amin Malekpour

Daniel Murphy

Proceedings of the 22nd IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2019

Approximate Integer and Floating-Point Dividers with Near-Zero Error Bias.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

RFTC: Runtime Frequency Tuning Countermeasure Using FPGA Dynamic Reconfiguration to Mitigate Power Analysis Attacks.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018

Minimally Biased Multipliers for Approximate Integer and Floating-Point Multiplication.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Conference Reports: Report on the 2017 International Conference on Computer-Aided Design (ICCAD).

[BibT_eX]

[DOI]

R. Iris Bahar

David Z. Pan

IEEE Des. Test, 2018

EETD: An Energy Efficient Design for Runtime Hardware Trojan Detection in Untrusted Network-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

CryptoBlaze: A partially homomorphic processor with multiple instructions and non-deterministic encryption support.

[BibT_eX]

[DOI]

Florencia Irena

Daniel Murphy

Vikkitharan Gnanasambandapillai

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

MESGA: An MPSoC based embedded system solution for short read genome alignment.

[BibT_eX]

[DOI]

Arash Bayat

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017

Network-on-Chip Design.

[BibT_eX]

[DOI]

Proceedings of the Handbook of Hardware/Software Codesign., 2017

Partial Dynamic Element Matching Technique for Digital-to-Analog Converters Used for Digital Harmonic-Cancelling Sine-Wave Synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Fine-Grained Checkpoint Recovery for Application-Specific Instruction-Set Processors.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2017

iCETD: An improved tag generation design for memory data authentication in embedded processor systems.

[BibT_eX]

[DOI]

Integr., 2017

Improved VCF normalization for accurate VCF comparison.

[BibT_eX]

[DOI]

Arash Bayat

Bruno Gaëta

Bioinform., 2017

NORA: Algorithmic Balancing without Pre-charge to Thwart Power Analysis Attacks.

[BibT_eX]

[DOI]

Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

Social Presence in Social Media: Persuasion, Design and Discourse.

[BibT_eX]

[DOI]

Proceedings of the 2017 ACM SIGMIS Conference on Computers and People Research, 2017

TrojanGuard: Simple and Effective Hardware Trojan Mitigation Techniques for Pipelined MPSoCs.

[BibT_eX]

[DOI]

Amin Malekpour

Proceedings of the 54th Annual Design Automation Conference, 2017

Hardware approximate computing: how, why, when and where? (special session).

[BibT_eX]

[DOI]

Proceedings of the 2017 International Conference on Compilers, 2017

DoSGuard: Protecting pipelined MPSoCs against hardware Trojan based DoS attacks.

[BibT_eX]

[DOI]

Amin Malekpour

Proceedings of the 28th IEEE International Conference on Application-specific Systems, 2017

2016

Switchable cache: utilising dark silicon for application specific cache optimisations.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2016

Editorial Introduction of New Editor-in-Chief and Associate Editors.

[BibT_eX]

[DOI]

IEEE Embed. Syst. Lett., 2016

Dark Silicon: From Embedded to HPC Systems (Dagstuhl Seminar 16052).

[BibT_eX]

[DOI]

Dagstuhl Reports, 2016

Processor Design for Soft Errors: Challenges and State of the Art.

[BibT_eX]

[DOI]

ACM Comput. Surv., 2016

Self-timed automatic test pattern generation for null convention logic.

[BibT_eX]

[DOI]

Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016

The effect of amplitude resolution and mismatch on a digital-to-analog converter used for digital harmonic-cancelling sine-wave synthesis.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

RECORD: Reducing register traffic for checkpointing in embedded processors.

[BibT_eX]

[DOI]

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Does it sound as it claims: a detailed side-channel security analysis of QuadSeal countermeasure.

[BibT_eX]

[DOI]

Shivam Bhasin

Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

Improving tag generation for memory data authentication in embedded processor systems.

[BibT_eX]

[DOI]

Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015

Exploring Multilevel Cache Hierarchies in Application Specific MPSoCs.

[BibT_eX]

[DOI]

Isuru Nawinne

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

SecureD: A Secure Dual Core Embedded Processor.

[BibT_eX]

[DOI]

CoRR, 2015

ARGUS: A Framework for Rapid Design and Prototype of Heterogeneous Multicore Systems in FPGA.

[BibT_eX]

[DOI]

Proceedings of the 28th International Conference on VLSI Design, 2015

Dark Silicon: From Computation to Communication.

[BibT_eX]

[DOI]

Muhammad Usman Karim Khan

Siddharth Garg

Proceedings of the 9th International Symposium on Networks-on-Chip, 2015

Side channel attacks in embedded systems: A tale of hostilities and deterrence.

[BibT_eX]

[DOI]

Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

ARCHER: Communication-based predictive architecture selection for application specific multiprocessor Systems-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Design of a digital harmonic-cancelling sine-wave synthesizer with 100 MHz output frequency, 43.5 dB SFDR, and 2.26 mW power.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

RAPITIMATE: Rapid performance estimation of pipelined processing systems containing shared memory.

[BibT_eX]

[DOI]

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Sequential C-code to distributed pipelined heterogeneous MPSoC synthesis for streaming applications.

[BibT_eX]

[DOI]

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

E-pipeline: elastic hardware/software pipelines on a many-core fabric.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Dynamic reconfigurable puncturing for secure wireless communication.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Malleable NoC: dark silicon inspired adaptable Network-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

SuperNet: multimode interconnect architecture for manycore chips.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual Design Automation Conference, 2015

QuadSeal: Quadruple algorithmic symmetrizing countermeasure against power based side-channel attacks.

[BibT_eX]

[DOI]

Proceedings of the 2015 International Conference on Compilers, 2015

ADAPT: An adaptive manycore methodology for software pipelined applications.

[BibT_eX]

[DOI]

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

Speeding up single pass simulation of PLRUt caches.

[BibT_eX]

[DOI]

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014

Performance Estimation of Pipelined MultiProcessor System-on-Chips (MPSoCs).

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2014

Energy-Efficient Adaptive Pipelined MPSoCs for Multimedia Applications.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Reconfigurable Convolutional Codec for Physical Layer Communication Security Application.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE Military Communications Conference, 2014

A simple digital architecture for a harmonic-cancelling sine-wave synthesizer.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Advanced modes in AES: Are they safe from power analysis based side channel attacks?

[BibT_eX]

[DOI]

Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

Mapping programs for execution on pipelined MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE Symposium on Embedded Systems for Real-time Multimedia, 2014

Hardware-based fast exploration of cache hierarchies in application specific MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Flexible and scalable implementation of H.264/AVC encoder for multiple resolutions using ASIPs.

[BibT_eX]

[DOI]

Hong Chinh Doan

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

MASH{fifo}: A Hardware-Based Multiple Cache Simulator for Rapid FIFO Cache Analysis.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

FALCON: A Framework for HierarchicAL Computation of Metrics for CompONent-Based Parameterized SoCs.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

darkNoC: Designing Energy-Efficient Network-on-Chip with Multi-Vt Cells for Dark Silicon.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Dark silicon as a challenge for hardware/software co-design.

[BibT_eX]

[DOI]

Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis, 2014

A scorchingly fast FPGA-based Precise L1 LRU cache simulator.

[BibT_eX]

[DOI]

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

SDG2KPN: System Dependency Graph to function-level KPN generation of legacy code for MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

Pipelined Multiprocessor System-on-Chip for Multimedia.

[BibT_eX]

[DOI]

Springer, ISBN: 978-3-319-01112-7, 2014

2013

MAPro: A Tiny Processor for Reconfigurable Baseband Modulation Mapping.

[BibT_eX]

[DOI]

Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

A Study on Instruction-set Selection Using Multi-application Based Application Specific Instruction-set Processors.

[BibT_eX]

[DOI]

Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

A case study on exploration of last-level cache for energy reduction in DDR3 DRAM.

[BibT_eX]

[DOI]

Proceedings of the 2nd Mediterranean Conference on Embedded Computing, 2013

Dynamic encryption key design and management for memory data encryption in embedded systems.

[BibT_eX]

[DOI]

Mei Hong

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

A double-width algorithmic balancing to prevent power analysis Side Channel Attacks in AES.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

Variable increment step based reconfigurable interleaver for multimode communication application.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Latency-constrained binding of data flow graphs to energy conscious GALS-based MPSoCs.

[BibT_eX]

[DOI]

Isuru Nawinne

Thannirmalai Somu Muthukaruppan

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Energy-aware synthesis of application specific MPSoCs.

[BibT_eX]

[DOI]

Tulika Mitra

Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

DHASER: dynamic heterogeneous adaptation for soft-error resiliency in ASIP-based multi-core systems.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Previous messages provide the key to achieve shannon capacity in a wiretap channel.

[BibT_eX]

[DOI]

Shahid Mehraj Shah

Vinod Sharma

Proceedings of the IEEE International Conference on Communications, 2013

DRMA: dynamically reconfigurable MPSoC architecture.

[BibT_eX]

[DOI]

Kewal K. Saluja

Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

A novel intermittent fault Markov model for deep sub-micron processors.

[BibT_eX]

[DOI]

Babak Saghaie

Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

Analyzing the thermal hotspots in FPGA-based embedded systems.

[BibT_eX]

[DOI]

Hussam Amrouch

Thomas Ebi

Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

System-level optimization of on-chip communication using express links for throughput constrained MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the 11th IEEE Symposium on Embedded Systems for Real-time Multimedia, 2013

An extremely compact JPEG encoder for adaptive embedded systems.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

CSER: HW/SW configurable soft-error resiliency for application specific instruction-set processors.

[BibT_eX]

[DOI]

Muhammad Shafique

Semeen Rehman

Proceedings of the Design, Automation and Test in Europe, 2013

Reconfigurable pipelined coprocessor for multi-mode communication transmission.

[BibT_eX]

[DOI]

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

XDRA: exploration and optimization of last-level cache for energy reduction in DDR DRAMs.

[BibT_eX]

[DOI]

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

RASTER: runtime adaptive spatial/temporal error resiliency for embedded processors.

[BibT_eX]

[DOI]

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Run-time adaption for highly-complex multi-core systems.

[BibT_eX]

[DOI]

Vijaykrishnan Narayanan

Jürgen Teich

Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2013

RExCache: Rapid exploration of unified last-level cache.

[BibT_eX]

[DOI]

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

Multi-mode pipelined MPSoCs for streaming applications.

[BibT_eX]

[DOI]

Daniel Witono

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012

Randomized Instruction Injection to Counter Power Analysis Attacks.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2012

A Rapid Methodology for Multi-mode Communication Circuit Generation.

[BibT_eX]

[DOI]

Proceedings of the 25th International Conference on VLSI Design, 2012

CoRaS: A multiprocessor key corruption and random round swapping for power analysis side channel attacks: A DES case study.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Fine-grained hardware/software methodology for process migration in MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Reli: Hardware/software Checkpoint and Recovery scheme for embedded processors.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

DIMSim: a rapid two-level cache simulation approach for deadline-based MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

2011

Architectural Frameworks for Security and Reliability of MPSoCs.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2011

Configurable Multimode Embedded Floating-Point Units for FPGAs.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2011

A hybrid hardware-software technique to improve reliability in embedded processors.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2011

Multiprocessor information concealment architecture to prevent power analysis-based side channel attacks.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2011

Realizing Cycle Accurate Processor Memory Simulation via Interface Abstraction.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

A Hardware/Software Countermeasure and a Testing Framework for Cache Based Side Channel Attacks.

[BibT_eX]

[DOI]

Proceedings of the IEEE 10th International Conference on Trust, 2011

System-level application-aware dynamic power management in adaptive pipelined MPSoCs for multimedia.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

CIPARSim: Cache intersection property assisted rapid single-pass FIFO cache simulation technique.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Multi-ASIP based parallel and scalable implementation of motion estimation kernel for high definition videos.

[BibT_eX]

[DOI]

Hong Chinh Doan

Proceedings of the 9th IEEE Symposium on Embedded Systems for Real-Time Multimedia, 2011

Low-power adaptive pipelined MPSoCs for multimedia: an H.264 video encoder case study.

[BibT_eX]

[DOI]

Proceedings of the 48th Design Automation Conference, 2011

2010

Rapid Design Space Exploration of Application Specific Heterogeneous Pipelined Multiprocessor Systems.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Shifted gray encoding to reduce instruction memory address bus switching for low-power embedded systems.

[BibT_eX]

[DOI]

J. Syst. Archit., 2010

CASES 2009 guest editor's introduction.

[BibT_eX]

[DOI]

Des. Autom. Embed. Syst., 2010

LOP: A packet classification architecture with higher throughput and lower power consumption than TCAM.

[BibT_eX]

[DOI]

Des. Autom. Embed. Syst., 2010

Improved Architectures for Range Encoding in Packet Classification System.

[BibT_eX]

[DOI]

Proceedings of The Ninth IEEE International Symposium on Networking Computing and Applications, 2010

RACE: A Rapid, ArChitectural Simulation and Synthesis Framework for Embedded Processors.

[BibT_eX]

[DOI]

Proceedings of the Distributed, Parallel and Biologically Inspired Systems, 2010

Fidelity metrics for estimation models.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Optimal WCET-aware code selection for scratchpad memory.

[BibT_eX]

[DOI]

Hui Wu

Jingling Xue

Proceedings of the 10th International conference on Embedded software, 2010

Rapid runtime estimation methods for pipelined MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

Dueling CLOCK: Adaptive cache replacement policy based on the CLOCK algorithm.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

DEW: A fast level 1 cache simulation approach for embedded processors with FIFO replacement policy.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

SCUD: a fast single-pass L1 cache simulation approach for embedded processors with round-robin replacement policy.

[BibT_eX]

[DOI]

Proceedings of the 47th Design Automation Conference, 2010

Optimal synthesis of latency and throughput constrained pipelined MPSoCs targeting streaming applications.

[BibT_eX]

[DOI]

Proceedings of the 8th International Conference on Hardware/Software Codesign and System Synthesis, 2010

2009

Provably correct on-chip communication: A formal approach to automatic protocol converter synthesis.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2009

Custom Floating-Point Unit Generation for Embedded Systems.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

HMP-ASIPs: heterogeneous multi-pipeline application-specific instruction-set processors.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2009

Security and Dependability of Embedded Systems: A Computer Architects' Perspective.

[BibT_eX]

[DOI]

Vijaykrishnan Narayanan

Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

LOP_RE: Range encoding for low power packet classification.

[BibT_eX]

[DOI]

Proceedings of the 34th Annual IEEE Conference on Local Computer Networks, 2009

Flexible multi-mode embedded floating-point unit for field programmable gate arrays.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

CUFFS: An instruction count based architectural framework for security of MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

A design flow for application specific heterogeneous pipelined multiprocessor systems.

[BibT_eX]

[DOI]

Proceedings of the 46th Design Automation Conference, 2009

LOP: a novel SRAM-based architecture for low power and high throughput packet classification.

[BibT_eX]

[DOI]

Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009

SuSeSim: a fast simulation strategy to find optimal L1 cache configuration for embedded systems.

[BibT_eX]

[DOI]

Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009

HitME: low power Hit MEmory buffer for embedded systems.

[BibT_eX]

[DOI]

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008

Energy Driven Application Self-Adaptation at Run-time.

[BibT_eX]

[DOI]

J. Comput., 2008

Architectural Exploration of Heterogeneous Multiprocessor Systems for JPEG.

[BibT_eX]

[DOI]

Andrea Erdos

Int. J. Parallel Program., 2008

Low-Impact Processor for Dynamic Runtime Power Management.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2008

Guest editorial for special issue on embedded system security.

[BibT_eX]

[DOI]

Tilman Wolf

Des. Autom. Embed. Syst., 2008

Embedded systems security - an overview.

[BibT_eX]

[DOI]

Tilman Wolf

Des. Autom. Embed. Syst., 2008

Anatomy of Differential Power Analysis for AES.

[BibT_eX]

[DOI]

Naeill Aldon

Proceedings of the SYNASC 2008, 2008

MUTE-AES: a multiprocessor architecture to prevent power analysis based side channel attack of the AES algorithm.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

A Formal Approach To The Protocol Converter Problem.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2008

SHIELD: a software hardware design methodology for security and reliability of MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the 45th Design Automation Conference, 2008

Rapid application specific floating-point unit generation with bit-alignment.

[BibT_eX]

[DOI]

Proceedings of the 45th Design Automation Conference, 2008

LOCS: a low overhead profiler-driven design flow for security of MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, 2008

Synthesis of heterogeneous pipelined multiprocessor systems using ILP: jpeg case study.

[BibT_eX]

[DOI]

Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, 2008

NoCOUT : NoC topology generation with mixed packet-switched and point-to-point networks.

[BibT_eX]

[DOI]

Jeremy Chan

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007

A Power-Efficient 5.6-GHz Process-Compensated CMOS Frequency Divider.

[BibT_eX]

[DOI]

Ivan Siu-Chuang Lu

Neil Weste

IEEE Trans. Circuits Syst. II Express Briefs, 2007

Energy Driven Application SelfAdaptation.

[BibT_eX]

[DOI]

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Instruction trace compression for rapid instruction cache simulation.

[BibT_eX]

[DOI]

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Automatic application specific floating-point unit generation.

[BibT_eX]

[DOI]

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Design Methodology for Pipelined Heterogeneous Multiprocessor System.

[BibT_eX]

[DOI]

Proceedings of the 44th Design Automation Conference, 2007

RIJID: Random Code Injection to Mask Power Analysis based Side Channel Attacks.

[BibT_eX]

[DOI]

Proceedings of the 44th Design Automation Conference, 2007

Ensuring secure program execution in multiprocessor embedded systems: a case study.

[BibT_eX]

[DOI]

Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007

A smart random code injection to mask power analysis based side channel attacks.

[BibT_eX]

[DOI]

Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007

CLIPPER: Counter-based Low Impact Processor Power Estimation at Run-time.

[BibT_eX]

[DOI]

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006

Exploiting statistical information for implementation of instruction scratchpad memory in embedded system.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2006

ADC Precision Requirement for Digital Ultra-Wideband Receivers with Sublinear Front-Ends: A Power and Performance Perspective.

[BibT_eX]

[DOI]

Ivan Siu-Chuang Lu

Neil Weste

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Minimising the Energy Consumption of Real-Time Tasks with Precedence Constraints on a Single Processor.

[BibT_eX]

[DOI]

Hui Wu

Proceedings of the Embedded and Ubiquitous Computing, International Conference, 2006

Customization of application specific heterogeneous multi-pipeline processors.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

IMPRES: integrated monitoring for processor reliability and security.

[BibT_eX]

[DOI]

Proceedings of the 43rd Design Automation Conference, 2006

Heterogeneous multiprocessor implementations for JPEG: : a case study.

[BibT_eX]

[DOI]

Andrea Erdos

Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

Hardware assisted pre-emptive control flow checking for embedded processors to improve reliability.

[BibT_eX]

[DOI]

Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

Application specific forwarding network and instruction encoding for multi-pipe ASIPs.

[BibT_eX]

[DOI]

Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

Finding optimal L1 cache configuration for embedded systems.

[BibT_eX]

[DOI]

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

A novel instruction scratchpad memory optimization method based on concomitance metric.

[BibT_eX]

[DOI]

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005

Instruction code mapping for performance increase and energy reduction in embedded computer systems.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2005

The effect of receiver front-end non-linearity on DS-UWB systems operating in the 3 to 4 GHz band.

[BibT_eX]

[DOI]

Ivan Siu-Chuang Lu

Neil Weste

Proceedings of the IEEE Wireless Communications and Networking Conference, 2005

Rapid Embedded Hardware/Software System Generation.

[BibT_eX]

[DOI]

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Balancing System Level Pipelines with Stage Voltage Scaling.

[BibT_eX]

[DOI]

Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

NoCEE: energy macro-model extraction methodology for network on chip routers.

[BibT_eX]

[DOI]

Jeremy Chan

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Novel architecture for loop acceleration: a case study.

[BibT_eX]

[DOI]

Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005

Micro embedded monitoring for security in application specific instruction-set processors.

[BibT_eX]

[DOI]

Sayed Mohammad Kia

Proceedings of the 2005 International Conference on Compilers, 2005

Battery-aware instruction generation for embedded processors.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

NoCGEN: A Template Based Reuse Methodology for Networks on Chip Architecture.

[BibT_eX]

[DOI]

Jeremy Chan

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Hardware/software managed scratchpad memory for embedded system.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

A quantitative study and estimation models for extensible instructions in embedded processors.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

MINCE: Matching INstructions Using Combinational Equivalence for Extensible Processor.

[BibT_eX]

[DOI]

Proceedings of the 2004 Design, 2004

Dual-pipeline heterogeneous ASIP design.

[BibT_eX]

[DOI]

Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004

2003

Specification and Design of Multi-Million Gate SOCs.

[BibT_eX]

[DOI]

Loganath Ramachandran

Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

INSIDE: INstruction Selection/Identification & Design Exploration for Extensible Processors.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Rapid Configuration and Instruction Selection for an ASIP: A Case Study.

[BibT_eX]

[DOI]

Proceedings of the 2003 Design, 2003

Multi-parametric improvements for embedded systems using code-placement and address bus coding.

[BibT_eX]

[DOI]

Haris Lekatsas

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

Rapid Configuration & Instruction Selection for an ASIP: A Case Study.

[BibT_eX]

[DOI]

Proceedings of the Embedded Software for SoC, 2003

2002

SWASAD: An ASIC Design for High Speed DNA Sequence Matching.

[BibT_eX]

[DOI]

Tony Han

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

2001

I-CoPES: Fast Instruction Code Placement for Embedded Systems to Improve Performance and Energy Efficiency.

[BibT_eX]

[DOI]

Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Code placement in hardware/software co-synthesis to improve performance and reduce cost.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000

Profiling in the ASP codesign environment.

[BibT_eX]

[DOI]

Matthew F. Parkinson

Peter L. Bartlett

J. Syst. Archit., 2000

High-level model of a WDMA passive optical bus for a reconfigurable multiprocessor system.

[BibT_eX]

[DOI]

Vince E. Boros

Aleksandar D. Rakic

Proceedings of the 37th Conference on Design Automation, 2000

Voltage reduction of application-specific heterogeneous multiprocessor systems for power minimisation.

[BibT_eX]

[DOI]

Allan Rae

Proceedings of ASP-DAC 2000, 2000

1998

Application-Specific Heterogeneous Multiprocessor Synthesis Using Differential-Evolution.

[BibT_eX]

[DOI]

Allan Rae

Proceedings of the 11th International Symposium on System Synthesis, 1998

Power Reduction in Pipelines.

[BibT_eX]

[DOI]

Proceedings of the ASP-DAC '98, 1998

HW-SW Co-Synthesis: The Present and The Future (Embedded Tutorial).

[BibT_eX]

[DOI]

Proceedings of the ASP-DAC '98, 1998

Unrolling Loops With Indeterminate Loop Counts in System Level Pipelines.

[BibT_eX]

[DOI]

Proceedings of the ASP-DAC '98, 1998

1997

Power consumption in CMOS combinational logic blocks at high frequencies.

[BibT_eX]

[DOI]

Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

1995

Profiling in the ASP codesign environment.

[BibT_eX]

[DOI]

Matthew F. Parkinson

Proceedings of the 8th International Symposium on System Synthesis (ISSS 1995), 1995

Reclocking for high-level synthesis.

[BibT_eX]

[DOI]

Pradip K. Jha

Nikil D. Dutt

Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995

1994

Novel architectures for TSC/CD and SFS/SCD synchronous controllers.

[BibT_eX]

[DOI]

Sayed Mohammad Kia

Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994

Design automation of self checking circuits.

[BibT_eX]

[DOI]

Sayed Mohammad Kia

Proceedings of the Proceedings EURO-DAC'94, 1994

1991

SPOT: A computer aided digital design system

[BibT_eX]

[DOI]