Sri Parameswaran

According to our database1, Sri Parameswaran authored at least 182 papers between 1994 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2019
SWARAM: Portable Energy and Cost Efficient Embedded System for Genomic Processing.
ACM Trans. Embedded Comput. Syst., 2019

Pairwise alignment of nucleotide sequences using maximal exact matches.
BMC Bioinformatics, 2019

Hardware Trojan Detection and Recovery in MPSoCs via On-line Application Specific Testing.
Proceedings of the 22nd IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2019

Approximate Integer and Floating-Point Dividers with Near-Zero Error Bias.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

RFTC: Runtime Frequency Tuning Countermeasure Using FPGA Dynamic Reconfiguration to Mitigate Power Analysis Attacks.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
Minimally Biased Multipliers for Approximate Integer and Floating-Point Multiplication.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Conference Reports: Report on the 2017 International Conference on Computer-Aided Design (ICCAD).
IEEE Design & Test, 2018

EETD: An Energy Efficient Design for Runtime Hardware Trojan Detection in Untrusted Network-on-Chip.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

CryptoBlaze: A partially homomorphic processor with multiple instructions and non-deterministic encryption support.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

MESGA: An MPSoC based embedded system solution for short read genome alignment.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
Network-on-Chip Design.
Proceedings of the Handbook of Hardware/Software Codesign., 2017

Partial Dynamic Element Matching Technique for Digital-to-Analog Converters Used for Digital Harmonic-Cancelling Sine-Wave Synthesis.
IEEE Trans. on Circuits and Systems, 2017

Fine-Grained Checkpoint Recovery for Application-Specific Instruction-Set Processors.
IEEE Trans. Computers, 2017

iCETD: An improved tag generation design for memory data authentication in embedded processor systems.
Integration, 2017

Improved VCF normalization for accurate VCF comparison.
Bioinformatics, 2017

NORA: Algorithmic Balancing without Pre-charge to Thwart Power Analysis Attacks.
Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

TrojanGuard: Simple and Effective Hardware Trojan Mitigation Techniques for Pipelined MPSoCs.
Proceedings of the 54th Annual Design Automation Conference, 2017

Hardware approximate computing: how, why, when and where? (special session).
Proceedings of the 2017 International Conference on Compilers, 2017

DoSGuard: Protecting pipelined MPSoCs against hardware Trojan based DoS attacks.
Proceedings of the 28th IEEE International Conference on Application-specific Systems, 2017

2016
Switchable cache: utilising dark silicon for application specific cache optimisations.
IET Computers & Digital Techniques, 2016

Editorial Introduction of New Editor-in-Chief and Associate Editors.
Embedded Systems Letters, 2016

Dark Silicon: From Embedded to HPC Systems (Dagstuhl Seminar 16052).
Dagstuhl Reports, 2016

Processor Design for Soft Errors: Challenges and State of the Art.
ACM Comput. Surv., 2016

The effect of amplitude resolution and mismatch on a digital-to-analog converter used for digital harmonic-cancelling sine-wave synthesis.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

RECORD: Reducing register traffic for checkpointing in embedded processors.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Does it sound as it claims: a detailed side-channel security analysis of QuadSeal countermeasure.
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

Improving tag generation for memory data authentication in embedded processor systems.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
Exploring Multilevel Cache Hierarchies in Application Specific MPSoCs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2015

SecureD: A Secure Dual Core Embedded Processor.
CoRR, 2015

ARGUS: A Framework for Rapid Design and Prototype of Heterogeneous Multicore Systems in FPGA.
Proceedings of the 28th International Conference on VLSI Design, 2015

Dark Silicon: From Computation to Communication.
Proceedings of the 9th International Symposium on Networks-on-Chip, 2015

Side channel attacks in embedded systems: A tale of hostilities and deterrence.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

ARCHER: Communication-based predictive architecture selection for application specific multiprocessor Systems-on-Chip.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Design of a digital harmonic-cancelling sine-wave synthesizer with 100 MHz output frequency, 43.5 dB SFDR, and 2.26 mW power.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

RAPITIMATE: Rapid performance estimation of pipelined processing systems containing shared memory.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Sequential C-code to distributed pipelined heterogeneous MPSoC synthesis for streaming applications.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

E-pipeline: elastic hardware/software pipelines on a many-core fabric.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Dynamic reconfigurable puncturing for secure wireless communication.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Malleable NoC: dark silicon inspired adaptable Network-on-Chip.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

SuperNet: multimode interconnect architecture for manycore chips.
Proceedings of the 52nd Annual Design Automation Conference, 2015

QuadSeal: Quadruple algorithmic symmetrizing countermeasure against power based side-channel attacks.
Proceedings of the 2015 International Conference on Compilers, 2015

ADAPT: An adaptive manycore methodology for software pipelined applications.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

Speeding up single pass simulation of PLRUt caches.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Performance Estimation of Pipelined MultiProcessor System-on-Chips (MPSoCs).
IEEE Trans. Parallel Distrib. Syst., 2014

Energy-Efficient Adaptive Pipelined MPSoCs for Multimedia Applications.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2014

A simple digital architecture for a harmonic-cancelling sine-wave synthesizer.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Advanced modes in AES: Are they safe from power analysis based side channel attacks?
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

Mapping programs for execution on pipelined MPSoCs.
Proceedings of the 12th IEEE Symposium on Embedded Systems for Real-time Multimedia, 2014

Hardware-based fast exploration of cache hierarchies in application specific MPSoCs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Flexible and scalable implementation of H.264/AVC encoder for multiple resolutions using ASIPs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

MASH{fifo}: A Hardware-Based Multiple Cache Simulator for Rapid FIFO Cache Analysis.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

FALCON: A Framework for HierarchicAL Computation of Metrics for CompONent-Based Parameterized SoCs.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

darkNoC: Designing Energy-Efficient Network-on-Chip with Multi-Vt Cells for Dark Silicon.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Dark silicon as a challenge for hardware/software co-design.
Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis, 2014

A scorchingly fast FPGA-based Precise L1 LRU cache simulator.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

SDG2KPN: System Dependency Graph to function-level KPN generation of legacy code for MPSoCs.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

Pipelined Multiprocessor System-on-Chip for Multimedia.
Springer, ISBN: 978-3-319-01112-7, 2014

2013
MAPro: A Tiny Processor for Reconfigurable Baseband Modulation Mapping.
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

A Study on Instruction-set Selection Using Multi-application Based Application Specific Instruction-set Processors.
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

Dynamic encryption key design and management for memory data encryption in embedded systems.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

A double-width algorithmic balancing to prevent power analysis Side Channel Attacks in AES.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

Variable increment step based reconfigurable interleaver for multimode communication application.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Latency-constrained binding of data flow graphs to energy conscious GALS-based MPSoCs.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Energy-aware synthesis of application specific MPSoCs.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

DHASER: dynamic heterogeneous adaptation for soft-error resiliency in ASIP-based multi-core systems.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

DRMA: dynamically reconfigurable MPSoC architecture.
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

A novel intermittent fault Markov model for deep sub-micron processors.
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

Analyzing the thermal hotspots in FPGA-based embedded systems.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

System-level optimization of on-chip communication using express links for throughput constrained MPSoCs.
Proceedings of the 11th IEEE Symposium on Embedded Systems for Real-time Multimedia, 2013

An extremely compact JPEG encoder for adaptive embedded systems.
Proceedings of the Design, Automation and Test in Europe, 2013

CSER: HW/SW configurable soft-error resiliency for application specific instruction-set processors.
Proceedings of the Design, Automation and Test in Europe, 2013

Reconfigurable pipelined coprocessor for multi-mode communication transmission.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

XDRA: exploration and optimization of last-level cache for energy reduction in DDR DRAMs.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

RASTER: runtime adaptive spatial/temporal error resiliency for embedded processors.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Run-time adaption for highly-complex multi-core systems.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2013

RExCache: Rapid exploration of unified last-level cache.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

Multi-mode pipelined MPSoCs for streaming applications.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
Randomized Instruction Injection to Counter Power Analysis Attacks.
ACM Trans. Embedded Comput. Syst., 2012

A Rapid Methodology for Multi-mode Communication Circuit Generation.
Proceedings of the 25th International Conference on VLSI Design, 2012

CoRaS: A multiprocessor key corruption and random round swapping for power analysis side channel attacks: A DES case study.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Fine-grained hardware/software methodology for process migration in MPSoCs.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Reli: Hardware/software Checkpoint and Recovery scheme for embedded processors.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

DIMSim: a rapid two-level cache simulation approach for deadline-based MPSoCs.
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

2011
Architectural Frameworks for Security and Reliability of MPSoCs.
IEEE Trans. VLSI Syst., 2011

Configurable Multimode Embedded Floating-Point Units for FPGAs.
IEEE Trans. VLSI Syst., 2011

A hybrid hardware-software technique to improve reliability in embedded processors.
ACM Trans. Embedded Comput. Syst., 2011

Multiprocessor information concealment architecture to prevent power analysis-based side channel attacks.
IET Computers & Digital Techniques, 2011

Realizing Cycle Accurate Processor Memory Simulation via Interface Abstraction.
Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

A Hardware/Software Countermeasure and a Testing Framework for Cache Based Side Channel Attacks.
Proceedings of the IEEE 10th International Conference on Trust, 2011

System-level application-aware dynamic power management in adaptive pipelined MPSoCs for multimedia.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

CIPARSim: Cache intersection property assisted rapid single-pass FIFO cache simulation technique.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Multi-ASIP based parallel and scalable implementation of motion estimation kernel for high definition videos.
Proceedings of the 9th IEEE Symposium on Embedded Systems for Real-Time Multimedia, 2011

Low-power adaptive pipelined MPSoCs for multimedia: an H.264 video encoder case study.
Proceedings of the 48th Design Automation Conference, 2011

2010
Rapid Design Space Exploration of Application Specific Heterogeneous Pipelined Multiprocessor Systems.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2010

Shifted gray encoding to reduce instruction memory address bus switching for low-power embedded systems.
Journal of Systems Architecture - Embedded Systems Design, 2010

CASES 2009 guest editor's introduction.
Design Autom. for Emb. Sys., 2010

LOP: A packet classification architecture with higher throughput and lower power consumption than TCAM.
Design Autom. for Emb. Sys., 2010

Improved Architectures for Range Encoding in Packet Classification System.
Proceedings of The Ninth IEEE International Symposium on Networking Computing and Applications, 2010

RACE: A Rapid, ArChitectural Simulation and Synthesis Framework for Embedded Processors.
Proceedings of the Distributed, Parallel and Biologically Inspired Systems, 2010

Fidelity metrics for estimation models.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Optimal WCET-aware code selection for scratchpad memory.
Proceedings of the 10th International conference on Embedded software, 2010

Rapid runtime estimation methods for pipelined MPSoCs.
Proceedings of the Design, Automation and Test in Europe, 2010

Dueling CLOCK: Adaptive cache replacement policy based on the CLOCK algorithm.
Proceedings of the Design, Automation and Test in Europe, 2010

DEW: A fast level 1 cache simulation approach for embedded processors with FIFO replacement policy.
Proceedings of the Design, Automation and Test in Europe, 2010

SCUD: a fast single-pass L1 cache simulation approach for embedded processors with round-robin replacement policy.
Proceedings of the 47th Design Automation Conference, 2010

Optimal synthesis of latency and throughput constrained pipelined MPSoCs targeting streaming applications.
Proceedings of the 8th International Conference on Hardware/Software Codesign and System Synthesis, 2010

2009
Provably correct on-chip communication: A formal approach to automatic protocol converter synthesis.
ACM Trans. Design Autom. Electr. Syst., 2009

Custom Floating-Point Unit Generation for Embedded Systems.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2009

HMP-ASIPs: heterogeneous multi-pipeline application-specific instruction-set processors.
IET Computers & Digital Techniques, 2009

Security and Dependability of Embedded Systems: A Computer Architects' Perspective.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

LOP_RE: Range encoding for low power packet classification.
Proceedings of the 34th Annual IEEE Conference on Local Computer Networks, 2009

Flexible multi-mode embedded floating-point unit for field programmable gate arrays.
Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

CUFFS: An instruction count based architectural framework for security of MPSoCs.
Proceedings of the Design, Automation and Test in Europe, 2009

A design flow for application specific heterogeneous pipelined multiprocessor systems.
Proceedings of the 46th Design Automation Conference, 2009

LOP: a novel SRAM-based architecture for low power and high throughput packet classification.
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009

SuSeSim: a fast simulation strategy to find optimal L1 cache configuration for embedded systems.
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009

HitME: low power Hit MEmory buffer for embedded systems.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
Energy Driven Application Self-Adaptation at Run-time.
JCP, 2008

Architectural Exploration of Heterogeneous Multiprocessor Systems for JPEG.
International Journal of Parallel Programming, 2008

Low-Impact Processor for Dynamic Runtime Power Management.
IEEE Design & Test of Computers, 2008

Guest editorial for special issue on embedded system security.
Design Autom. for Emb. Sys., 2008

Embedded systems security - an overview.
Design Autom. for Emb. Sys., 2008

Anatomy of Differential Power Analysis for AES.
Proceedings of the SYNASC 2008, 2008

MUTE-AES: a multiprocessor architecture to prevent power analysis based side channel attack of the AES algorithm.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

A Formal Approach To The Protocol Converter Problem.
Proceedings of the Design, Automation and Test in Europe, 2008

SHIELD: a software hardware design methodology for security and reliability of MPSoCs.
Proceedings of the 45th Design Automation Conference, 2008

Rapid application specific floating-point unit generation with bit-alignment.
Proceedings of the 45th Design Automation Conference, 2008

LOCS: a low overhead profiler-driven design flow for security of MPSoCs.
Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, 2008

Synthesis of heterogeneous pipelined multiprocessor systems using ILP: jpeg case study.
Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, 2008

NoCOUT : NoC topology generation with mixed packet-switched and point-to-point networks.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
A Power-Efficient 5.6-GHz Process-Compensated CMOS Frequency Divider.
IEEE Trans. on Circuits and Systems, 2007

Energy Driven Application SelfAdaptation.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Instruction trace compression for rapid instruction cache simulation.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Automatic application specific floating-point unit generation.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Design Methodology for Pipelined Heterogeneous Multiprocessor System.
Proceedings of the 44th Design Automation Conference, 2007

RIJID: Random Code Injection to Mask Power Analysis based Side Channel Attacks.
Proceedings of the 44th Design Automation Conference, 2007

Ensuring secure program execution in multiprocessor embedded systems: a case study.
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007

A smart random code injection to mask power analysis based side channel attacks.
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007

CLIPPER: Counter-based Low Impact Processor Power Estimation at Run-time.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
Exploiting statistical information for implementation of instruction scratchpad memory in embedded system.
IEEE Trans. VLSI Syst., 2006

ADC Precision Requirement for Digital Ultra-Wideband Receivers with Sublinear Front-Ends: A Power and Performance Perspective.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Minimising the Energy Consumption of Real-Time Tasks with Precedence Constraints on a Single Processor.
Proceedings of the Embedded and Ubiquitous Computing, International Conference, 2006

Customization of application specific heterogeneous multi-pipeline processors.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

IMPRES: integrated monitoring for processor reliability and security.
Proceedings of the 43rd Design Automation Conference, 2006

Heterogeneous multiprocessor implementations for JPEG: : a case study.
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

Hardware assisted pre-emptive control flow checking for embedded processors to improve reliability.
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

Application specific forwarding network and instruction encoding for multi-pipe ASIPs.
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

Finding optimal L1 cache configuration for embedded systems.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

A novel instruction scratchpad memory optimization method based on concomitance metric.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
Instruction code mapping for performance increase and energy reduction in embedded computer systems.
IEEE Trans. VLSI Syst., 2005

The effect of receiver front-end non-linearity on DS-UWB systems operating in the 3 to 4 GHz band.
Proceedings of the IEEE Wireless Communications and Networking Conference, 2005

Rapid Embedded Hardware/Software System Generation.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Balancing System Level Pipelines with Stage Voltage Scaling.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

NoCEE: energy macro-model extraction methodology for network on chip routers.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Novel architecture for loop acceleration: a case study.
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005

Micro embedded monitoring for security in application specific instruction-set processors.
Proceedings of the 2005 International Conference on Compilers, 2005

Battery-aware instruction generation for embedded processors.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
NoCGEN: A Template Based Reuse Methodology for Networks on Chip Architecture.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Hardware/software managed scratchpad memory for embedded system.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

A quantitative study and estimation models for extensible instructions in embedded processors.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

MINCE: Matching INstructions Using Combinational Equivalence for Extensible Processor.
Proceedings of the 2004 Design, 2004

Dual-pipeline heterogeneous ASIP design.
Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004

2003
Specification and Design of Multi-Million Gate SOCs.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

INSIDE: INstruction Selection/Identification & Design Exploration for Extensible Processors.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Rapid Configuration and Instruction Selection for an ASIP: A Case Study.
Proceedings of the 2003 Design, 2003

Multi-parametric improvements for embedded systems using code-placement and address bus coding.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

Rapid Configuration & Instruction Selection for an ASIP: A Case Study.
Proceedings of the Embedded Software for SoC, 2003

2002
SWASAD: An ASIC Design for High Speed DNA Sequence Matching.
Proceedings of the ASPDAC 2002 / VLSI Design 2002, 2002

2001
I-CoPES: Fast Instruction Code Placement for Embedded Systems to Improve Performance and Energy Efficiency.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Code placement in hardware/software co-synthesis to improve performance and reduce cost.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000
Profiling in the ASP codesign environment.
Journal of Systems Architecture, 2000

High-level model of a WDMA passive optical bus for a reconfigurable multiprocessor system.
Proceedings of the 37th Conference on Design Automation, 2000

Voltage reduction of application-specific heterogeneous multiprocessor systems for power minimisation.
Proceedings of ASP-DAC 2000, 2000

1998
Application-Specific Heterogeneous Multiprocessor Synthesis Using Differential-Evolution.
Proceedings of the 11th International Symposium on System Synthesis, 1998

Power Reduction in Pipelines.
Proceedings of the ASP-DAC '98, 1998

HW-SW Co-Synthesis: The Present and The Future (Embedded Tutorial).
Proceedings of the ASP-DAC '98, 1998

Unrolling Loops With Indeterminate Loop Counts in System Level Pipelines.
Proceedings of the ASP-DAC '98, 1998

1997
Power consumption in CMOS combinational logic blocks at high frequencies.
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

1995
Profiling in the ASP codesign environment.
Proceedings of the 8th International Symposium on System Synthesis (ISSS 1995), 1995

Reclocking for high-level synthesis.
Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995

1994
Novel architectures for TSC/CD and SFS/SCD synchronous controllers.
Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994

Design automation of self checking circuits.
Proceedings of the Proceedings EURO-DAC'94, 1994


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