Haris Javaid

Orcid: 0009-0008-3472-0803

According to our database1, Haris Javaid authored at least 41 papers between 2008 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
ApproxTrain: Fast Simulation of Approximate Multipliers for DNN Training and Inference.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023

A Primer on RecoNIC: RDMA-enabled Compute Offloading on SmartNIC.
CoRR, 2023

Demo: Enabling DNN Inference in the Network Data Plane.
Proceedings of the 6th on European P4 Workshop, 2023

2022
Improving Energy Efficiency of Permissioned Blockchains Using FPGAs.
Proceedings of the 28th IEEE International Conference on Parallel and Distributed Systems, 2022

Blockchain Machine: A Network-Attached Hardware Accelerator for Hyperledger Fabric.
Proceedings of the 42nd IEEE International Conference on Distributed Computing Systems, 2022

Efficient FPGA-based ECDSA Verification Engine For Permissioned Blockchains.
Proceedings of the FPGA '22: The 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Virtual Event, USA, 27 February 2022, 2022

2020
Hardware Trojan Mitigation in Pipelined MPSoCs.
ACM Trans. Design Autom. Electr. Syst., 2020

A Sub-Range Error Characterization based Selection Methodology for Approximate Arithmetic Units.
Proceedings of the 33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems, 2020

REALM: Reduced-Error Approximate Log-based Integer Multiplier.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

WEID: Worst-case Error Improvement in Approximate Dividers.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019
Optimizing Validation Phase of Hyperledger Fabric.
Proceedings of the 27th IEEE International Symposium on Modeling, 2019

Approximate Integer and Floating-Point Dividers with Near-Zero Error Bias.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

FastProxy: Hardware and Software Acceleration of Stratum Mining Proxy.
Proceedings of the Crypto Valley Conference on Blockchain Technology, 2019

2016
Switchable cache: utilising dark silicon for application specific cache optimisations.
IET Comput. Digit. Tech., 2016

2015
Exploring Multilevel Cache Hierarchies in Application Specific MPSoCs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

E-pipeline: elastic hardware/software pipelines on a many-core fabric.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Malleable NoC: dark silicon inspired adaptable Network-on-Chip.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

SuperNet: multimode interconnect architecture for manycore chips.
Proceedings of the 52nd Annual Design Automation Conference, 2015

ADAPT: An adaptive manycore methodology for software pipelined applications.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Performance Estimation of Pipelined MultiProcessor System-on-Chips (MPSoCs).
IEEE Trans. Parallel Distributed Syst., 2014

Energy-Efficient Adaptive Pipelined MPSoCs for Multimedia Applications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Hardware-based fast exploration of cache hierarchies in application specific MPSoCs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Flexible and scalable implementation of H.264/AVC encoder for multiple resolutions using ASIPs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

FALCON: A Framework for HierarchicAL Computation of Metrics for CompONent-Based Parameterized SoCs.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

darkNoC: Designing Energy-Efficient Network-on-Chip with Multi-Vt Cells for Dark Silicon.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Pipelined Multiprocessor System-on-Chip for Multimedia.
Springer, ISBN: 978-3-319-01112-7, 2014

2013
A case study on exploration of last-level cache for energy reduction in DDR3 DRAM.
Proceedings of the 2nd Mediterranean Conference on Embedded Computing, 2013

Energy-aware synthesis of application specific MPSoCs.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

System-level optimization of on-chip communication using express links for throughput constrained MPSoCs.
Proceedings of the 11th IEEE Symposium on Embedded Systems for Real-time Multimedia, 2013

XDRA: exploration and optimization of last-level cache for energy reduction in DDR DRAMs.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

RExCache: Rapid exploration of unified last-level cache.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

Multi-mode pipelined MPSoCs for streaming applications.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2011
System-level application-aware dynamic power management in adaptive pipelined MPSoCs for multimedia.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Multi-ASIP based parallel and scalable implementation of motion estimation kernel for high definition videos.
Proceedings of the 9th IEEE Symposium on Embedded Systems for Real-Time Multimedia, 2011

Low-power adaptive pipelined MPSoCs for multimedia: an H.264 video encoder case study.
Proceedings of the 48th Design Automation Conference, 2011

2010
Rapid Design Space Exploration of Application Specific Heterogeneous Pipelined Multiprocessor Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Fidelity metrics for estimation models.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Rapid runtime estimation methods for pipelined MPSoCs.
Proceedings of the Design, Automation and Test in Europe, 2010

Optimal synthesis of latency and throughput constrained pipelined MPSoCs targeting streaming applications.
Proceedings of the 8th International Conference on Hardware/Software Codesign and System Synthesis, 2010

2009
A design flow for application specific heterogeneous pipelined multiprocessor systems.
Proceedings of the 46th Design Automation Conference, 2009

2008
Synthesis of heterogeneous pipelined multiprocessor systems using ILP: jpeg case study.
Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, 2008


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