Itsuo Takanami
According to our database1,
Itsuo Takanami
authored at least 96 papers
between 1976 and 2025.
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Bibliography
2025
Springer Briefs in Computer Science, Springer, ISBN: 978-981-96-1538-4, 2025
2022
Trans. Comput. Sci., 2022
2021
Self-restructuring of Mesh-Connected Processor Arrays with Spares Assigned on Rotated Orthogonal Side.
Trans. Comput. Sci., 2021
2019
A Built-In Circuit for Self-reconfiguring Mesh-Connected Processor Arrays with Spares on Diagonal.
Trans. Comput. Sci., 2019
2018
Restructuring Mesh-Connected Processor Arrays with Spares on Four Sides by Orthogonal Side Rotation.
Proceedings of the 23rd IEEE Pacific Rim International Symposium on Dependable Computing, 2018
Degradable Restructuring of Mesh-Connected Processor Arrays with Spares on Orthogonal Sides.
Proceedings of the 23rd IEEE Pacific Rim International Symposium on Dependable Computing, 2018
2017
A Built-in Circuit for Self-Repairing Mesh-Connected Processor Arrays with Spares on Diagonal.
Proceedings of the 22nd IEEE Pacific Rim International Symposium on Dependable Computing, 2017
2016
A Built-in Self-repair Circuit for Restructuring Mesh-Connected Processor Arrays by Direct Spare Replacement.
Trans. Comput. Sci., 2016
2015
An FPGA-Based Multiple-Weight-and-Neuron-Fault Tolerant Digital Multilayer Perceptron (Full Version).
Trans. Comput. Sci., 2015
2014
Multilayer Perceptrons Which Are Tolerant to Multiple Faults and Learnings to Realize Them.
Trans. Comput. Sci., 2014
Proceedings of the IEEE 8th International Symposium on Embedded Multicore/Manycore SoCs, 2014
2013
An FPGA-based multiple-weight-and-neuron-fault tolerant digital multilayer perceptron.
Neurocomputing, 2013
2012
A Built-in Circuit for Self-Repairing Mesh-Connected Processor Arrays by Direct Spare Replacement.
Proceedings of the IEEE 18th Pacific Rim International Symposium on Dependable Computing, 2012
2011
Trans. Comput. Sci., 2011
2010
SIGARCH Comput. Archit. News, 2010
2009
Novel Value Injection Learning Methods Which Make Multilayer Neural Networks Multiple-Weight-and-Neuron-Fault Tolerant.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2009
An Implementation of a Fault-Tolerant 2D Systolic Array on FPGAs and Its Evaluation.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2009
2008
Learning Algorithms Which Make Multilayer Neural Networks Multiple-Weight-and-Neuron-Fault Tolerant.
IEICE Trans. Inf. Syst., 2008
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008
2006
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006
2004
Self-Reconfiguring of 1½-Track-Switch Mesh Arrays with Spares on One Row and One Column by Simple Built-in Circuit.
IEICE Trans. Inf. Syst., 2004
2002
An Extreme Value Injection Approach with Reduced Learning Time to Make MLNs Multiple-Weight-Fault Tolerant.
Proceedings of the 9th Pacific Rim International Symposium on Dependable Computing (PRDC 2002), 2002
2001
Analytical Results for Reconfiguration of E-11/2- Track Switch Torus Arrays with Multiple Fault Types.
Proceedings of the 8th Pacific Rim International Symposium on Dependable Computing (PRDC 2001), 2001
Built-in Self-Reconfiguring Systems for Fault Tolerant Mesh-Connected Processor Arrays by Direct Spare Replacement.
Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001
2000
Fault-Tolerant Processor Arrays Based on the 1½-Track Switches with Flexible Spare Distributions.
IEEE Trans. Computers, 2000
A System for Efficiently Self-Reconstructing 1½-Track Switch Torus Arrays.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2000
Proceedings of the 5th International Symposium on Parallel Architectures, 2000
Proceedings of the IEEE-INNS-ENNS International Joint Conference on Neural Networks, 2000
Built-in Self-Reconfiguring Systems for Mesh-Connected Processor Arrays with Spares on Two Rows/Columns.
Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 2000
1999
Fault Tolerant Processor Arrays Based on 1 1/2-Track Switch with Generalized Spare Distributions.
Proceedings of the 1999 International Symposium on Parallel Architectures, 1999
1997
Proceedings of the 1997 International Symposium on Parallel Architectures, 1997
A Polynomial Time Algorithm for Reconfiguring the 1 1/2 Track-Switch Model with PE and Bus faults.
Proceedings of the 1997 International Symposium on Parallel Architectures, 1997
Self-reconstruction of mesh-arrays with 1 1/2 -track switches by digital neural circuits.
Proceedings of the 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 1997
Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997
1996
Proceedings of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1996
1995
Optimal Simulation of Two-Dimensional Alternating Finite Automata by Three-Way Nondeterministic Turing Machines.
Theor. Comput. Sci., 1995
Int. J. Pattern Recognit. Artif. Intell., 1995
Int. J. Pattern Recognit. Artif. Intell., 1995
Proceedings of the 1995 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1995
1994
Inf. Sci., 1994
Int. J. Pattern Recognit. Artif. Intell., 1994
1993
Construction of fault-tolerant mesh-connected highly parallel computer and its performance analysis.
Syst. Comput. Jpn., 1993
A note on three-dimensional alternating Turing machines with space smaller than log m.
Inf. Sci., 1993
Inf. Process. Lett., 1993
1992
A Relationship Between Nondeterministic Turing Machines and 1-Inkdot Turing Machines with Small Space.
Inf. Process. Lett., 1992
Int. J. Pattern Recognit. Artif. Intell., 1992
Int. J. Found. Comput. Sci., 1992
Proceedings of the Parallel Image Analysis, Second International Conference, 1992
Proceedings of the Parallel Image Analysis, Second International Conference, 1992
1991
Theor. Comput. Sci., 1991
Int. J. Found. Comput. Sci., 1991
1990
1989
Proceedings of the A Perspective in Theoretical Computer Science, 1989
Proceedings of the Array Grammars, Patterns and Recognizers, 1989
Deterministic Two-Dimensional On-Line Tessellation Acceptors are Equivalent to Two-Way Two-Dimensional Alternating Finite Automata Through 180°-Rotation.
Theor. Comput. Sci., 1989
Theor. Comput. Sci., 1989
One-Dimensional Bounded Cellular Acceptor with Rotated Inputs. A Relationship between ∧ and ∨ Types.
Syst. Comput. Jpn., 1989
Lower Bounds for Language Recognition on Two-Dimensional Alternating Multihead Machines.
J. Comput. Syst. Sci., 1989
1988
Proceedings of the Machines, 1988
1987
Syst. Comput. Jpn., 1987
Hierarchical properties of the κ -neighborhood template A-type 2-dimensional bounded cellular acceptor.
Syst. Comput. Jpn., 1987
1986
Relationship between the accepting powers of (k, <i>l</i>)-neighborhood template δ-type one-dimensional bounded cellular acceptors and other types of two-dimensional automata.
Syst. Comput. Jpn., 1986
Relationships of accepting powers between cellular space with bounded number of state-changes and other automata.
Syst. Comput. Jpn., 1986
1985
Alternating On-Line Turing Machines with Only Universal States and Small Space Bounds.
Theor. Comput. Sci., 1985
A space-hierarchy result on two-dimensional alternating Turing machines with only universal states.
Inf. Sci., 1985
1983
Theor. Comput. Sci., 1983
A Relationship between Two-Dimensional Finite Automata and Three-Way Tape-Bounded Two-Dimensional Turing Machines.
Theor. Comput. Sci., 1983
Connected pictures are not recognizable by deterministic two-dimensional on-line tessellation acceptors.
Comput. Vis. Graph. Image Process., 1983
1982
Inf. Control., 1982
Proceedings of the 14th Annual ACM Symposium on Theory of Computing, 1982
1980
Nonclosure property of nondeterministic two-dimensional finite automata under cyclic closure.
Inf. Sci., 1980
Inf. Sci., 1980
Inf. Process. Lett., 1980
1979
Closure properties of three-way and four-way tape-bounded two-dimensional turing machines.
Inf. Sci., 1979
1978
A note on closure properties of the classes of sets accepted by tape-bounded two-dimensional turing machines.
Inf. Sci., 1978
1976