Ivailo M. Nedelchev

According to our database, Ivailo M. Nedelchev authored at least 5 papers between 1994 and 1997.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of four.

1997

Power Compiler: A Gate-Level Power Optimization and Synthesis System.

Benjamin Chen, Ivailo M. Nedelchev

Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

1995

Asynchronous VLSI design.

Ivailo M. Nedelchev

PhD thesis, 1995

Low-latency asynchronous FIFO buffers.

Jelio Todorov Yantchev, C. G. Huang, Mark B. Josephs, Ivailo M. Nedelchev

Proceedings of the Second Working Conference on Asynchronous Design Methodologies, 1995

1994

Basic building blocks for asynchronous packet routers.

Ivailo M. Nedelchev, Chris R. Jesshope

Proceedings of the Fourth Great Lakes Symposium on Design Automation of High Performance VLSI Systems, 1994

Asynchronous packet routers.

Chris R. Jesshope, Ivailo M. Nedelchev

Proceedings of the Workshop on Interconnection Networks and Mapping and Scheduling Parallel Computations, 1994