Mark B. Josephs

According to our database1, Mark B. Josephs
  • authored at least 34 papers between 1986 and 2007.
  • has a "Dijkstra number"2 of three.

Timeline

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In proceedings 
Article 
PhD thesis 
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Links

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Bibliography

2007
Controllable Delay-Insensitive Processes.
Fundam. Inform., 2007

Gate-level modelling and verification of asynchronous circuits using CSPM and FDR.
Proceedings of the 13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2007), 2007

2006
Verification and Implementation of Delay-Insensitive Processes in Restrictive Environments.
Fundam. Inform., 2006

Asynchronous Packet-Switching for Networks-on-Chip.
Proceedings of the Sixth International Conference on Application of Concurrency to System Design (ACSD 2006), 2006

2005
Controllable Delay-Insensitive Processes and their Reflection, Interaction and Factorisation.
Proceedings of the Fifth International Conference on Application of Concurrency to System Design (ACSD 2005), 2005

2004
Modelling and verification of delay-insensitive circuits using CCS and the Concurrency Workbench.
Inf. Process. Lett., 2004

Decomposing specifications with concurrent outputs to resolve state coding conflicts in asynchronous logic synthesis.
Proceedings of the 41th Design Automation Conference, 2004

Models for Data-Flow Sequential Processes.
Proceedings of the Communicating Sequential Processes: The First 25 Years, 2004

Verification and Implementation of Delay-Insensitive Processes in Restrictive Environments.
Proceedings of the 4th International Conference on Application of Concurrency to System Design (ACSD 2004), 2004

2003
An Analysis of Determinacy Using a Trace-Theoretic Model of Asynchronous Circuits.
Proceedings of the 9th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2003), 2003

2002
Optimal Two-Level Delay - Insensitive Implementation of Logic Functions.
Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

A Programming Approach to the Design of Asynchronous Logic Blocks.
Proceedings of the Concurrency and Hardware Design, Advances in Petri Nets, 2002

2000
Delay-Insensitive Interface Specification and Synthesis.
Proceedings of the 2000 Design, 2000

1998
Protocol Specification, Testing and Verification XV, by Piotr Dembinski and Marek Sredniawa (Editors), Chapman and Hall, 1996 (Book Review).
Softw. Test., Verif. Reliab., 1998

Formal Derivation of a Loadable Asynchronous Counter.
Proceedings of the Mathematics of Program Construction, 1998

1997
The Use of SI-Algebra in the Design of Sequencer Circuits.
Formal Asp. Comput., 1997

1996
CMOS design of the tree arbiter element.
IEEE Trans. VLSI Syst., 1996

Some limitations to speed-independence in asynchronous circuits.
Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '96), 1996

1995
Low-latency asynchronous FIFO buffers.
Proceedings of the Second Working Conference on Asynchronous Design Methodologies, 1995

Sequencer circuits for VLSI programming.
Proceedings of the Second Working Conference on Asynchronous Design Methodologies, 1995

1994
Specifying Distributed CICS in Z: Accessing Local and Remote Resources (Short Communication).
Formal Asp. Comput., 1994

Formal design of an asynchronous DSP counterflow pipeline: a case study in handshake algebra.
Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems, 1994

1993
Implementing a Stack as a Delay-insensitive Circuit.
Proceedings of the Asynchronous Design Methodologies, Proceedings of the IFIP WG10.5 Working Conference on Asynchronous Design Methodologies, Manchester, UK, 31 March, 1993

Normal Form in a Delay-Insensitive Algebra.
Proceedings of the Asynchronous Design Methodologies, Proceedings of the IFIP WG10.5 Working Conference on Asynchronous Design Methodologies, Manchester, UK, 31 March, 1993

1992
Receptive Process Theory.
Acta Inf., 1992

High-Level Design of an Asynchronous Packet-Routing Chip.
Proceedings of the Designing Correct Circuits, 1992

1990
An Algebra for Delay-Insensitive Circuits.
Proceedings of the Computer-Aided Verification, 1990

Delay-Insensitive Circuits: An Algebraic Approach to their Design.
Proceedings of the CONCUR '90, 1990

An Algebra for Delay-Insensitive Circuits.
Proceedings of the Computer Aided Verification, 2nd International Workshop, 1990

1989
The Semantics of Lazy Functional Languages.
Theor. Comput. Sci., 1989

1988
The Data Refinement Calculator for Z Specifications.
Inf. Process. Lett., 1988

A State-Based Approach to Communicating Processes.
Distributed Computing, 1988

1986
Functional programming with side-effects.
PhD thesis, 1986

Functional Programming with Side-Effects.
Sci. Comput. Program., 1986


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