Chris R. Jesshope

According to our database1, Chris R. Jesshope authored at least 86 papers between 1980 and 2014.

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Bibliography

2014
On-chip traffic regulation to reduce coherence protocol cost on a microthreaded many-core architecture with distributed caches.
ACM Trans. Embedded Comput. Syst., 2014

Cache-based high-level simulation of microthreaded many-core architectures.
J. Syst. Archit., 2014

Signature-based high-level simulation of microthreaded many-core architectures.
Proceedings of the 4th International Conference On Simulation And Modeling Methodologies, 2014

Analytical-Based High-Level Simulation of the Microthreaded Many-Core Architectures.
Proceedings of the 22nd Euromicro International Conference on Parallel, 2014

A fault detection mechanism in a Data-flow scheduled Multithreaded processor.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Rethread: A Low-Cost Transient Fault Recovery Scheme for Multithreaded Processors.
Proceedings of the Ninth International Conference on Availability, 2014

2013
Apple-CORE: Harnessing general-purpose many-cores with hardware concurrency management.
Microprocess. Microsystems, 2013

MGSim - Simulation tools for multi-core processor architectures
CoRR, 2013

MGSim - A simulation environment for multi-core research and education.
Proceedings of the 2013 International Conference on Embedded Computer Systems: Architectures, 2013

On-demand thread-level fault detection in a concurrent programming environment.
Proceedings of the 2013 International Conference on Embedded Computer Systems: Architectures, 2013

2012
Collecting signatures to model latency tolerance in high-level simulations of microthreaded cores.
Proceedings of the 2012 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, 2012

Apple-CORE: Microgrids of SVP Cores - Flexible, General-Purpose, Fine-Grained Hardware Concurrency Management.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

2011
High Level Simulation of SVP Many-Core Systems.
Parallel Process. Lett., 2011

Engineering Concurrent Software Guided by Statistical Performance Analysis.
Proceedings of the Applications, Tools and Techniques on the Road to Exascale Computing, Proceedings of the conference ParCo 2011, 31 August, 2011

Mapping Distributed S-Net on the 48-core Intel SCC processor.
Proceedings of the 3rd Many-core Applications Research Community (MARC) Symposium. Proceedings of the 3rd MARC Symposium, 2011

Efficient Memory Copy Operations on the 48-core Intel SCC Processor.
Proceedings of the 3rd Many-core Applications Research Community (MARC) Symposium. Proceedings of the 3rd MARC Symposium, 2011

A Micro Threading Based Concurrency Model for Parallel Computing.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

2010
On the Compilation of a Language for General Concurrent Target Architectures.
Parallel Process. Lett., 2010

Towards scalable I/O on a many-core architecture.
Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, 2010

An Operating System Strategy for General-purpose Parallel Computing on Many-core Architectures.
Proceedings of the High Performance Computing: From Grids and Clouds to Exascale, 2010

Resource-Agnostic Programming for Many-Core Microgrids.
Proceedings of the Euro-Par 2010 Parallel Processing Workshops, 2010

2009
The implementation of an SVP many-core processor and the evaluation of its memory architecture.
SIGARCH Comput. Archit. News, 2009

An implementation of the SANE Virtual Processor using POSIX threads.
J. Syst. Archit., 2009

Implementation and evaluation of a microthread architecture.
J. Syst. Archit., 2009

Making multi-cores mainstream - from security to scalability.
Proceedings of the Parallel Computing: From Multicores and GPU's to Petascale, 2009

HPPC 2009 Panel: Are Many-Core Computer Vendors on Track?
Proceedings of the Euro-Par 2009, 2009

Evaluating CMPs and Their Memory Architecture.
Proceedings of the Architecture of Computing Systems, 2009

2008
Operating Systems in silicon and the Dynamic Management of Resources in Many-Core Chips.
Parallel Process. Lett., 2008

An Architecture and Protocol for the Management of Resources in Ubiquitous and Heterogeneous Systems Based on the SVP Model of Concurrency.
Proceedings of the Embedded Computer Systems: Architectures, 2008

Introduction to Programming Multicores.
Proceedings of the Embedded Computer Systems: Architectures, 2008

A general model of concurrency and its implementation as many-core dynamic RISC processors.
Proceedings of the 2008 International Conference on Embedded Computer Systems: Architectures, 2008

Building a Concurrency and Resource Allocation Model into a Processor's ISA.
Proceedings of the Euro-Par 2008 Workshops, 2008

The Verification of the On-Chip COMA Cache Coherence Protocol.
Proceedings of the Algebraic Methodology and Software Technology, 2008

Concurrency engineering.
Proceedings of the 13th Asia-Pacific Computer Systems Architecture Conference, 2008

2007
Asynchronous arbiter for micro-threaded chip multiprocessors.
J. Syst. Archit., 2007

Strategies for Compiling µ TC to Novel Chip Multiprocessors.
Proceedings of the Embedded Computer Systems: Architectures, 2007

Formalizing SANE Virtual Processor in Thread Algebra.
Proceedings of the Formal Methods and Software Engineering, 2007

On-Chip COMA Cache-Coherence Protocol for Microgrids of Microthreaded Cores.
Proceedings of the Euro-Par 2007 Workshops: Parallel Processing, 2007

High Level Modelling and Design For a Microthreaded Scheduler to Support Microgrids.
Proceedings of the 2007 IEEE/ACS International Conference on Computer Systems and Applications (AICCSA 2007), 2007

2006
Microthreading a Model for Distributed Instruction-level Concurrency.
Parallel Process. Lett., 2006

Guest Editor's Introduction (Part 2).
Int. J. Parallel Program., 2006

Special issue on Micro-grids - Guest Editor Introduction.
Int. J. Parallel Program., 2006

Supporting Microthread Scheduling and Synchronisation in CMPs.
Int. J. Parallel Program., 2006

Instruction Level Parallelism through Microthreading - A Scalable Approach to Chip Multiprocessors.
Comput. J., 2006

A Model for the Design and Programming of Multi-cores.
Proceedings of the High Performance Computing and Grids in Action, 2006

Scalable and Partitionable Asynchronous Arbiter for Micro-threaded Chip Multiprocessors.
Proceedings of the Architecture of Computing Systems, 2006

muTC - An Intermediate Language for Programming Chip Multiprocessors.
Proceedings of the Advances in Computer Systems Architecture, 11th Asia-Pacific Conference, 2006

2005
The Challenges of Massive On-Chip Concurrency.
Proceedings of the Advances in Computer Systems Architecture, 10th Asia-Pacific Conference, 2005

2004
Scalable Instruction-Level Parallelism..
Proceedings of the Computer Systems: Architectures, 2004

A General Learning Management System Based on Schema-driven Methodology.
Proceedings of the IEEE International Conference on Advanced Learning Technologies, 2004

Microgrids - The exploitation of massive on-chip concurrency.
Proceedings of the Grid Computing: The New Frontier of High Performance Computing [post-proceedings of the High Performance Computing Workshop, 2004

2003
Web Services Technology and Learning Technology- A Web-Services Model for Constructing Decentralized Virtual Learning Environments.
Proceedings of the International Conference on Web Services, ICWS '03, June 23, 2003

Multi-threaded Microprocessors - Evolution or Revolution.
Proceedings of the Advances in Computer Systems Architecture, 2003

2001
Cost-Effective Multimedia in On-line Teaching.
J. Educ. Technol. Soc., 2001

Adaptivity in Web-based Educational System.
Proceedings of the Poster Proceedings of the Tenth International World Wide Web Conference, 2001

Technology Integrated Learning Environment - A Web-based Distance Learning System.
Proceedings of the Fifth IASTED International Conference Internet and Multimedia Systems and Applications (IMSA 2001), 2001

Topic 12: Routing and Communication in Interconnection Networks.
Proceedings of the Euro-Par 2001: Parallel Processing, 2001

Implementing an efficient vector instruction set in a chip multi-processor using micro-threaded pipelines.
Proceedings of the 6th Australasian Computer Systems Architecture Conference (ACSAC 2001), 2001

2000
Micro-Threading: A New Approach to Future RISC.
Proceedings of the 5th Australasian Computer Architecture Conference (ACAC 2000), 31 January, 2000

1999
Computers as Tutors: Solving the Crisis in Education.
J. Educ. Technol. Soc., 1999

Parallel Computer Architecture - What Is Its Future? Introduction.
Proceedings of the Euro-Par '99 Parallel Processing, 5th International Euro-Par Conference, Toulouse, France, August 31, 1999

1998
Multi-campus teaching using computer networks.
Proceedings of the ACM SIGCSE 3rd Australasian Conference on Computer Science Education, 1998

1997
Optical Interconnectivity in a Scalable Data-Parallel System.
J. Parallel Distributed Comput., 1997

Web based teaching: a minimalist approach.
Proceedings of the ACM SIGCSE 2nd Australasian Conference on Computer Science Education, 1997

1996
A FORTRAN 90 to F-code Compiler.
Proceedings of the UK Parallel '96 - Proceedings of the BCS PPSG Annual Conference, Surrey, 1996

Optical Interconnection hardware for scalable systems.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 1996

1995
Multiprocessing: Trade-offs in computation and communication : Vijay K Naik Kluwer Academic Publishers, Dordrecht, The Netherlands (1993) ISBN 0 7923 9370 8, Dfl 180.00, £65.50, pp224.
Microprocess. Microsystems, 1995

1994
Mechanized Reasoning and Hardware Design: C A R Hoare and M J C Gordon (Eds) Prentice Hall, Hemel Hempstead, UK (1992) ISBN 0 13 572405 8, £40, pp 151.
Microprocess. Microsystems, 1994

Mad-postman : A Look-ahead Message Propagation Method For Static Bidimensional Meshes.
Proceedings of the Second Euromicro Workshop on Parallel and Distributed Processing, 1994

Basic building blocks for asynchronous packet routers.
Proceedings of the Fourth Great Lakes Symposium on Design Automation of High Performance VLSI Systems, 1994

Asynchronous packet routers.
Proceedings of the Workshop on Interconnection Networks and Mapping and Scheduling Parallel Computations, 1994

1993
Latency Reduction in VLSI Routers.
Parallel Process. Lett., 1993

Experimental evaluation of Mad Postman bidimensional routing networks.
Microprocess. Microprogramming, 1993

The MP1 Network Chip and its Application to Parallel Computers.
Comput. J., 1993

The MP1 network chip.
Proceedings of the 1993 Euromicro Workshop on Parallel and Distributed Processing, 1993

1991
Simulation Facility of Distributed Memory System with "Mad Postman" Communication Network.
Proceedings of the Distributed Memory Computing, 2nd Euronean Conference, 1991

1989
Parallel program design: a foundation: Chandry, K M and Misra, J Addison-Wesley, Wokingham, UK (1988) £19.95 pp 516.
Microprocess. Microsystems, 1989

Editorial.
Microprocess. Microsystems, 1989

Parallel processing, the transputer and the future.
Microprocess. Microsystems, 1989

High Performance Communications in Processor Networks.
Proceedings of the 16th Annual International Symposium on Computer Architecture. Jerusalem, 1989

1988
Transputers and switches as objects in OCCAM.
Parallel Comput., 1988

MUNAP: an unusual computer with clear implications: Baba, TMicroprogrammable parallel computers MIT Press, Cambridge, MA, USA (1987) £26.95 pp 290.
Microprocess. Microsystems, 1988

Programming with active data.
Proceedings of the Parcella '88, 1988

1985
An Intelligent Pascal Editor for a Graphical Oriented Workstation.
Softw. Pract. Exp., 1985

1980
Some Results Concerning Data Routing in Array Processors.
IEEE Trans. Computers, 1980

The Implementation of Fast Radix 2 Transforms on Array Processors.
IEEE Trans. Computers, 1980


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