Jae-Kyung Wee
According to our database1,
Jae-Kyung Wee
authored at least 16 papers
between 2000 and 2013.
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Bibliography
2013
A Digitally-Controlled SMPS Using a Novel High-Resolution DPWM Generator Based on a Pseudo Relaxation-Oscillation Technique.
IEICE Trans. Electron., 2013
2012
One-chip multi-output SMPS using a shared digital controller and a pseudo relaxation oscillating technique.
Proceedings of the International SoC Design Conference, 2012
Current readout circuit using two-stage amplification method for 64-channel CNT arrays.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
2011
J. Circuits Syst. Comput., 2011
2008
Novel Method of Interconnect Worstcase Establishment with Statistically-Based Approaches.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008
2007
A Novel High-Speed and Low-Voltage CMOS Level-Up/Down Shifter Design for Multiple-Power and Multiple-Clock Domain Chips.
IEICE Trans. Electron., 2007
2006
IEICE Trans. Electron., 2006
2005
Low-Hardware-Cost Motion Estimation with Large Search Range for VLSI Multimedia Processors.
IEICE Trans. Inf. Syst., 2005
Proceedings of the Knowledge-Based Intelligent Information and Engineering Systems, 2005
Proceedings of the High Performance Computing, 2005
Proceedings of the Embedded and Ubiquitous Computing, 2005
2004
Low power motion estimator architecture with leakage power reduction in deep sub-micron SoC.
Proceedings of the Second IASTED International Conference on Circuits, 2004
2002
A post-package bit-repair scheme using static latches with bipolar-voltage programmable antifuse circuit for high-density DRAMs.
IEEE J. Solid State Circuits, 2002
A low-jitter wide-range skew-calibrated dual-loop DLL using antifuse circuitry for high-speed DRAM.
IEEE J. Solid State Circuits, 2002
IEEE J. Solid State Circuits, 2002
2000
IEEE J. Solid State Circuits, 2000