Kyeong-Sik Min
Orcid: 0000-0002-1518-7037
According to our database1,
Kyeong-Sik Min
authored at least 41 papers
between 2001 and 2024.
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Bibliography
2024
Assessing the Role of Yarn Placement in Plated Knit Strain Sensors: A Detailed Study of Their Electromechanical Properties and Applicability in Bending Cycle Monitoring.
Sensors, March, 2024
2023
Proceedings of the 20th International SoC Design Conference, 2023
Hardware-Specific Optimization for Mapping of Convolutional Neural Networks to Memristor Crossbars.
Proceedings of the 15th IEEE International Conference on ASIC, 2023
2022
Quantization, training, parasitic resistance correction, and programming techniques of memristor-crossbar neural networks for edge intelligence.
Neuromorph. Comput. Eng., 2022
Proceedings of the 11th International Conference on Modern Circuits and Systems Technologies, 2022
2021
Comparative Study on Quantization-Aware Training of Memristor Crossbars for Reducing Inference Power of Neural Networks at The Edge.
Proceedings of the International Joint Conference on Neural Networks, 2021
2020
Defect-Resilient Memristor Crossbar of Hierarchical Temporal Memory (HTM) Spatial Pooling for Near-IoT-Sensor Cognitive Computing.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020
2019
Non-Ideal Effects of Memristor-CMOS Hybrid Circuits for Realizing Multiple-Layer Neural Networks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
Defect-Tolerant and Energy-Efficient Training of Multi-Valued and Binary Memristor Crossbars for Near-Sensor Cognitive Computing.
Proceedings of the 13th IEEE International Conference on ASIC, 2019
Proceedings of the Handbook of Memristor Networks., 2019
2016
Microelectron. J., 2016
Memristor circuits and systems for future computing and bio-inspired information processing.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2016
Live demonstration: Memristor synaptic array with FPGA-implemented neurons for neuromorphic pattern recognition.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016
2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
2012
Sunlight-variation-adaptive charge pump circuit with self-reconfiguration for small-scale solar energy harvesting.
IEICE Electron. Express, 2012
2011
Oxide-Tunneling Leakage Suppressed SRAM for Sub-65-nm Very Large Scale Integrated Circuits.
J. Low Power Electron., 2011
Carry select adder with sub-block power gating for reducing active-mode leakage in sub-32-nm VLSIs.
IEICE Electron. Express, 2011
Dual-switch power gating revisited for small sleep energy loss and fast wake-up time in sub-45-nm nodes.
IEICE Electron. Express, 2011
Compact and efficient Maximum Power Point Tracking circuit for portable solar battery charger.
IEICE Electron. Express, 2011
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011
2009
Sub-1-V-Output CMOS bandgap reference circuit with small area and low power consumption.
IEICE Electron. Express, 2009
IEICE Electron. Express, 2009
Low-power read circuit with self-adjusted column pulse width for diode-switch resistive RAMs.
IEICE Electron. Express, 2009
IEICE Electron. Express, 2009
New word-line driving scheme for suppressing oxide-tunneling leakage in sub-65-nm SRAMs.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009
2008
Comparative Study on Leakage Current of Power-Gated SRAMs for 65-nm, 45-nm, 32-nm Technology Nodes.
J. Comput., 2008
IEICE Trans. Commun., 2008
IEICE Trans. Electron., 2008
Sense amplifier driving scheme with adaptive delay line for reducing peak current and driving time variations in deep-sub-micron DRAMs.
IEICE Electron. Express, 2008
2007
An Approach for Numerical Analysis of Differential Equation-Based Feeding Point Modeling of Electromagnetic Devices.
IEICE Trans. Commun., 2007
IEICE Trans. Electron., 2007
Comparative Study on SRAMs for Suppressing Both Oxide-Tunneling Leakage and Subthreshold Leakage in Sub-70-nm Leakage Dominant VLSIs.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007
2006
Leakage-suppressed clock-gating circuit with Zigzag Super Cut-off CMOS (ZSCCMOS) for leakage-dominant sub-70-nm and sub-1-V-V<sub>DD</sub> LSIs.
IEEE Trans. Very Large Scale Integr. Syst., 2006
2005
Row-by-Row Dynamic Source-Line Voltage Control (RRDSV) Scheme for Two Orders of Magnitude Leakage Current Reduction of Sub-1-V-<i>V<sub>DD</sub></i> SRAM's.
IEICE Trans. Electron., 2005
2004
A 66-333-MHz 12-mW register-controlled DLL with a single delay line and adaptive-duty-cycle clock dividers for production DDR SDRAMs.
IEEE J. Solid State Circuits, 2004
A large-current-output boosted voltage generator with non-overlapping clock control for sub-1-V memory applications.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
2002
A post-package bit-repair scheme using static latches with bipolar-voltage programmable antifuse circuit for high-density DRAMs.
IEEE J. Solid State Circuits, 2002
CMOS charge pumps using cross-coupled charge transfer switches with improved voltage pumping gain and low gate-oxide stress for low-voltage memory circuits.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
2001
IEEE J. Solid State Circuits, 2001