James D. Balfour

According to our database1, James D. Balfour authored at least 11 papers between 2006 and 2014.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2014
Author retrospective for design tradeoffs for tiled CMP on-chip networks.
Proceedings of the ACM International Conference on Supercomputing 25th Anniversary Volume, 2014

2013
A detailed and flexible cycle-accurate Network-on-Chip simulator.
Proceedings of the 2012 IEEE International Symposium on Performance Analysis of Systems & Software, 2013

2010
Fine-grain dynamic instruction placement for L0 scratch-pad memory.
Proceedings of the 2010 International Conference on Compilers, 2010

2009
Operand Registers and Explicit Operand Forwarding.
IEEE Comput. Archit. Lett., 2009

Elastic-buffer flow control for on-chip networks.
Proceedings of the 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 2009

2008
Efficient Embedded Computing.
Computer, 2008

Hierarchical Instruction Register Organization.
IEEE Comput. Archit. Lett., 2008

An Energy-Efficient Processor Architecture for Embedded Systems.
IEEE Comput. Archit. Lett., 2008

2007
Flattened Butterfly Topology for On-Chip Networks.
Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-40 2007), 2007

Register pointer architecture for efficient embedded processors.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
Design tradeoffs for tiled CMP on-chip networks.
Proceedings of the 20th Annual International Conference on Supercomputing, 2006


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